PSD835G2 datasheet(74/102 Pages) STMICROELECTRONICS

74 / 102 page

PSD835G2

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RESET TIMING AND DEVICE STATUS AT RESET

Power-Up Reset

Upon Power-up, the PSD requires a Reset (RE-

SET) pulse of duration tNLNH-PO (1ms minimum)

after VCC is steady. During this period, the device

loads internal configurations, clears some of the

registers and sets the Flash memory into Operat-

ing mode. After the rising edge of Reset (RESET),

the PSD remains in the Reset mode for an addi-

tional period, tOPR (120ns maximum), before the

first memory access is allowed.

The Flash memory is reset to the READ mode

upon Power-up. Sector Select (FS0-FS7 and

CSBOOT0-CSBOOT3) must all be Low, Write

Strobe (WR, CNTL0) High, during Power-Up Re-

set for maximum security of the data contents and

to remove the possibility of a byte being written on

the first edge of Write Strobe (WR, CNTL0). Any

Flash memory WRITE cycle initiation is prevented

automatically when VCC is below VLKO.

Warm Reset

Once the device is up and running, the device can

be reset with a pulse of a much shorter duration,

tNLNH (150ns minimum). The same tOPR period is

needed before the device is operational after

warm reset. Figure 33 shows the timing of the

Power-up and warm reset.

I/O Pin, Register and PLD Status at Reset

Table 47., page 75 shows the I/O pin, register and

PLD status during Power-Up Reset, warm reset

and Power-down mode. PLD outputs are always

valid during warm reset, and they are valid in Pow-

er-Up Reset once the internal PSD Configuration

bits are loaded. This loading of PSD is completed

typically long before VCC ramps up to operating

level. Once the PLD is active, the state of the out-

puts are determined by the equations specified in

PSDsoft.

Reset of Flash Memory Erase and Program

Cycles

A Reset (RESET) also resets the internal Flash

memory state machine. During a Flash memory

Program or Erase cycle, Reset (RESET) termi-

nates the cycle and returns the Flash memory to

the READ mode within a period of tNLNH-A (25µs

minimum).

Figure 33. Power-Up and Warm Reset (RESET) Timing

tNLNH-PO

tOPR

AI02866b

RESET

tNLNH

tNLNH-A

tOPR

VCC

CC(min)

Power-On Reset

Warm Reset

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