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PSD835G2 датащи(PDF) 77 Page - STMicroelectronics

номер детали PSD835G2
подробное описание детали  Flash PSD, 5V Supply, for 8-bit MCUs 4 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM
PDF  102 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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PSD835G2 датащи(HTML) 77 Page - STMicroelectronics

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PSD835G2
JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by an JTAG command received over the
four standard JTAG signals (TMS, TCK, TDI, and
TDO). They are used to speed Program and Erase
cycles by indicating status on PSD signals instead
of having to scan the status out serially using the
standard JTAG channel. See Application Note
AN1153.
TERR indicates if an error has occurred when
erasing a sector or programming a Byte in Flash
memory. This signal goes Low (active) when an
Error condition occurs, and stays Low until a spe-
cial JTAG command is executed or a chip Reset
(RESET)
pulse
is
received
after
an
“ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy de-
scribed
in
the
section
entitled
Ready/Busy
(PE4), page 26. TSTAT is High when the PSD de-
vice is in READ mode (primary and secondary
Flash memory contents can be read). TSTAT is
Low when Flash memory Program or Erase cycles
are in progress, and also when data is being writ-
ten to the secondary Flash memory.
TSTAT and TERR can be configured as open-
drain type signals during a JTAG command.
Security and Flash memory Protection
When the Security Bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a Full
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the part to a
non-secured blank state. The Security Bit can be
set in PSDsoft.
All primary and secondary Flash memory sectors
can individually be sector protected against era-
sures. The Sector Protect Bits can be set in PSD-
soft.
Table 48. JTAG Port Signals
Port E Pin
JTAG Signals
Description
PE0
TMS
Mode Select
PE1
TCK
Clock
PE2
TDI
Serial Data In
PE3
TDO
Serial Data Out
PE4
TSTAT
Status
PE5
TERR
Error Flag



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