PSD835G2 datasheet(34/102 Pages) STMICROELECTRONICS

34 / 102 page

PSD835G2

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SPECIFIC FEATURES

Flash Memory Sector Protect

Each primary and secondary Flash memory sector

can be separately protected against Program and

Erase cycles. Sector Protection provides addition-

al data security because it disables all Program or

Erase cycles. This mode can be activated through

the JTAG/ISP Port or a Device Programmer.

Sector protection can be selected for each sector

using the PSDsoft program. This automatically

protects selected sectors when the device is pro-

grammed through the JTAG Port or a Device Pro-

grammer.

Flash

memory

sectors

can

unprotected to allow updating of their contents us-

ing the JTAG Port or a Device Programmer. The

MCU can read (but cannot change) the sector pro-

tection bits.

Any attempt to program or erase a protected Flash

memory sector is ignored by the device. The Verify

operation results in a READ of the protected data.

The retention of the Protection status is thus en-

sured.

The sector protection status can be read by the

MCU through the primary and secondary Flash

memory protection registers (in the CSIOP block).

See Table 18., page 21 and Table 19., page 22.

Reset Flash

The Reset Flash instruction consists of one

WRITE cycle (see Table 28., page 27). It can also

be optionally preceded by the standard two

WRITE decoding cycles (writing AAh to AAAh and

55h to 554h).

It must be executed after:

– Reading the Flash Protection Status or Flash ID

using the Flash instruction.

– An Error condition has occurred (and the device

has set the Error Flag Bit (DQ5) to ’1’) during a

Flash memory Program or Erase cycle.

The Reset Flash instruction puts the Flash memo-

ry back into normal READ mode immediately. If an

Error condition has occurred (and the device has

set the Error Flag Bit (DQ5) to ’1’) the Flash mem-

ory is put back into normal READ mode within

µs of the Reset Flash instruction having been

issued. The Reset Flash instruction is ignored

when it is issued during a Program or Bulk Erase

cycle of the Flash memory. The Reset Flash in-

struction aborts any on-going Sector Erase cycle,

and returns the Flash memory to the normal READ

mode within 25

µs.

Reset (RESET) Signal

A pulse on Reset (RESET) aborts any cycle that is

in progress, and resets the Flash memory to the

READ mode. When the reset occurs during a Pro-

gram or Erase cycle, the Flash memory takes up

to 25

µs to return to the READ mode. It is recom-

mended that the Reset (RESET) pulse (except for

the one described in Power-Up Reset, page 74)

be at least 25

µs so that the Flash memory is al-

ways ready for the MCU to fetch the bootstrap in-

structions after the Reset cycle is complete.

SRAM

The SRAM is enabled when SRAM Select (RS0)

from the DPLD is High. SRAM Select (RS0) can

contain up to three product terms, allowing flexible

memory mapping.

The SRAM can be backed up using an external

battery. The external battery should be connected

to Voltage Stand-by (VSTBY, PE6). If you have an

external battery connected to the PSD, the con-

tents of the SRAM are retained in the event of a

power loss. The contents of the SRAM are re-

tained so long as the battery voltage remains at

2 V or greater. If the supply voltage falls below the

battery voltage, an internal power switch-over to

the battery occurs.

PE7 can be configured as an output that indicates

when power is being drawn from the external bat-

tery. Battery-on Indicator (VBATON, PE7) is High

when the supply voltage falls below the battery

voltage and the battery on Voltage Stand-by

(VSTBY, PE6) is supplying power to the internal

SRAM.

SRAM Select (RS0), Voltage Stand-by (VSTBY,

PC2) and Battery-on Indicator (VBATON, PC4) are

all configured using PSDsoft Express Configura-

tion.

The SRAM Select (RS0), VBATON and VSTBY are

all configured using PSDsoft.

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