PSD835G2 datasheet(12/102 Pages) STMICROELECTRONICS

12 / 102 page

PSD835G2

12/102

Reset

Active Low input. Resets I/O Ports, PLD macrocells and some of the Configuration

Registers and JTAG registers. Must be Low at Power-up. Reset also aborts the

Flash programming/erase cycle that is in progress.

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

I/O CMOS

or Open

Drain

These pins make up Port A. These port pins are configurable and can have the

following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellA0-7) outputs.

Inputs to the PLDs.

Latched, transparent or registered PLD input.

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

I/O CMOS

or Open

Drain

These pins make up Port B. These port pins are configurable and can have the

following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellB0-7) output.

Inputs to the PLDs.

Latched, transparent or registered PLD input.

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

I/O CMOS

or Open

Drain

These pins make up Port C. These port pins are configurable and can have the

following functions:

MCU I/O – write to or read from a standard output or input port.

External Chip Select (ECS0-7) output.

Latched, transparent or registered PLD input.

PD0

I/O CMOS

or Open

Drain

PD0 pin of Port D. This port pin can be configured to have the following functions:

ALE/AS input latches addresses on ADIO0-ADIO15 pins.

AS input latches addresses on ADIO0-ADIO15 pins on the rising edge.

Input to the PLDs.

Transparent PLD input.

PD1

I/O CMOS

or Open

Drain

PD1 pin of Port D. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

Input to the PLDs.

CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter,

and the CPLD AND Array.

PD2

I/O CMOS

or Open

Drain

PD2 pin of Port D. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

Input to the PLDs.

PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory

and I/O. When High, the PSD memory blocks are disabled to conserve power. The

trailing edge of CSI can be used to get the PSD out of power-down mode.

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Type

Description

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