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PSD835G2 датащи(PDF) 40 Page - STMicroelectronics

номер детали PSD835G2
подробное описание детали  Flash PSD, 5V Supply, for 8-bit MCUs 4 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM
PDF  102 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD835G2 датащи(HTML) 40 Page - STMicroelectronics

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Decode PLD (DPLD)
The DPLD, shown in Figure 14, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
–
8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each)
–
4 Sector Select (CSBOOT0-CSBOOT3)
signals for the secondary Flash memory (three
product terms each)
–
1 internal SRAM Select (RS0) signal (three
product terms)
–
1 internal CSIOP Select (PSD Configuration
Register) signal
–
1 JTAG Select signal (enables JTAG/ISP on
Port E)
–
2 internal Peripheral Select signals
(Peripheral I/O mode).
Figure 14. DPLD Logic Array
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
2. Additional address lines can be brought into PSD via Port A, B, C, D or F.
(INPUTS)
(32)
(8)
(16)
(1)
PDN (APD OUTPUT)
I /O PORTS (PORT A,B,C,F)
(8)
PGR0 - PGR7
(8)
MCELLA.FB7-FB0 (FEEDBACKS)
MCELLB.FB7-FB0 (FEEDBACKS)
A15-A0(1,2)
(4)
(3)
PD3-PD0 (ALE,CLKIN,CSI)
CNTRL2-CNTRL0 (READ/WRITE CONTROL SIGNALS)
(1)
(1)
RESET
RD_BSY
RS0
CSIOP
PSEL0
PSEL1
8 PRIMARY FLASH
MEMORY SECTOR
SELECTS
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O
MODE SELECT
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS7
3
3
3
3
3
3
3
3
3
3
3
3
3
JTAGSEL
AI02873E
FS1
FS2
FS3
FS6
FS5
FS4



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