PSD835G2 datasheet(72/102 Pages) STMICROELECTRONICS

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PSD835G2

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Other Power Saving Options

The PSD offers other reduced power saving op-

tions that are independent of the Power-down

mode. Except for the SRAM Standby and Chip Se-

lect Input (CSI, PD2) features, they are enabled by

setting bits in the PMMR0 and PMMR2 registers

(see Table 22., page 22 and Table 23., page 22

for a bit definition of the two registers).

PLD Power Management

The power and speed of the PLDs are controlled

by the Turbo Bit (Bit 3) in PMMR0. By setting the

bit to '1,' the Turbo mode is off and the PLDs con-

sume the specified standby current when the in-

puts are not switching for an extended time of

70ns. The propagation delay time is increased af-

ter the Turbo Bit is set to ’1’ (turned off) when the

inputs change at a composite frequency of less

than 15 MHz. When the Turbo Bit is reset to ’0’

(turned on), the PLDs run at full power and speed.

The Turbo Bit affects the PLD’s DC power, AC

power, and propagation delay. Refer to MAXI-

MUM RATING, page 81 for PLD timings.

Blocking MCU control signals with the bits of

PMMR2 can further reduce PLD AC power con-

sumption.

SRAM Standby Mode (Battery Backup). The

PSD supports a battery backup mode in which the

contents of the SRAM are retained in the event of

a power loss. The SRAM has a Voltage Standby

pin (VSTBY, PC2) that can be connected to an ex-

ternal battery. When VCC becomes lower than

VSTBY then the PSD automatically connects to

Voltage Stand-by (VSTBY, PC2) as a power source

to the SRAM. The SRAM Standby Current (ISTBY)

is typically 0.5µA. The SRAM data retention volt-

age is 2 V minimum. The Battery-on Indicator

(VBATON) can be routed to PE7. This signal indi-

cates when the VCC has dropped below VSTBY and

the SRAM is running on battery power.

PSD Chip Select Input (CSI, PD2)

PD2 of Port D can be configured in PSDsoft as the

PSD Chip Select Input (CSI). When Low, the sig-

nal selects and enables the internal (primary)

Flash memory, secondary Flash memory, SRAM,

and I/O blocks for READ or WRITE operations in-

volving the PSD. A High on PSD Chip Select Input

(CSI, PD2) disables the primary Flash memory,

secondary Flash memory, and SRAM, and reduc-

es the PSD power consumption. However, the

PLD and I/O signals remain operational when PSD

Chip Select Input (CSI, PD2) is High.

There may be a timing penalty when using PSD

Chip Select Input (CSI, PD2) depending on the

speed grade of the PSD that you are using. See

the timing parameter tSLQV in Table 64., page 93.

Input Clock

The PSD provides the option to turn off CLKIN

(PD1) to the PLD to save AC power consumption.

CLKIN (PD1) is an input to the PLD AND Array and

the Output Macrocells (OMC).

During Power-down mode, or, if CLKIN (PD1) is

not being used as part of the PLD logic equation,

the clock should be disabled to save AC power.

CLKIN (PD1) is disconnected from the PLD AND

Array or the Macrocells block by setting Bits 4 or 5

to a ’1’ in PMMR0.

Figure 32. Enable Power-down Flow Chart

Enable APD

Set PMMR0 Bit 1 = 1

PSD in Power

Down Mode

ALE/AS idle

for 15 CLKIN

clocks?

RESET

Yes

OPTIONAL

Disable desired inputs to PLD

by setting PMMR0 bits 4 and 5

and PMMR2 bit 0.

AI02892B

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