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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD835G2 датащи(PDF) 14 Page - STMicroelectronics |
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PSD835G2 датащи(HTML) 14 Page - STMicroelectronics |
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14 / 102 page  PSD835G2 14/102 PE7 78 I/O CMOS or Open Drain PE7 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. VBATON battery backup indicator output. Goes High when power is drawn from an external battery. PF0-PF7 31-38 I/O CMOS or Open Drain PF0 through PF7 pins of Port F. This port pins can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Input to the PLDs. Latched address outputs. As address A0-A3 inputs in 80C51XA mode. As data bus port (D07) in non-multiplexed bus configuration. PG0- PG7 8, 30, 49, 50, 70 I/O CMOS or Open Drain PG0 through PG7 pins of Port G. This port pins can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address outputs. VCC 9, 29, 69 Supply Voltage GND 8, 30, 49, 50, 70 Ground pins Pin Name Pin Type Description |
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