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PSD835G2 датащи(PDF) 95 Page - STMicroelectronics

номер детали PSD835G2
подробное описание детали  Flash PSD, 5V Supply, for 8-bit MCUs 4 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM
PDF  102 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD835G2 датащи(HTML) 95 Page - STMicroelectronics

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PSD835G2
Table 67. Power-down Timing
Note: 1. tCLCL is the period of CLKIN (PD1).
Figure 48. Reset (RESET) Timing
Table 68. Reset (Reset) Timing
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ mode.
Table 69. VSTBYON Timing
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.
Symbol
Parameter
Conditions
-70
-90
Unit
Min
Max
Min
Max
tLVDV
ALE Access Time from Power-down
80
90
ns
tCLWH
Maximum Delay from
APD Enable to Internal PDN Valid Signal
Using CLKIN (PD1)
15 * tCLCL
1
µs
Symbol
Parameter
Conditions
Min
Max
Unit
tNLNH
RESET Active Low Time 1
150
ns
tNLNH–PO
Power On Reset Active Low Time
1
ms
tNLNH–A
Warm Reset 2
25
µs
tOPR
RESET High to Operational Device
120
ns
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
VSTBY Detection to VSTBYON Output High
(Note 1)
20
µs
tBXBL
VSTBY Off Detection to VSTBYON Output Low
(Note 1)
20
µs
tNLNH-PO
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
tOPR
VCC
V
CC(min)
Power-On Reset
Warm Reset



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