ADP1052ACPZ-R7 datasheet(108/113 Pages) AD

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ADP1052

Data Sheet

Rev. B | Page 108 of 113

Table 194. Register 0xFE6E—OUTC and OUTD Adjustment Reference During Synchronization

Bits

Bit Name/Function

R/W

Description

tR4 adjustment reference

R/W

Setting this bit enables edge adjustment on the OUTD rising edge, tR4.

tR4 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

tF4 adjustment reference

R/W

Setting this bit enables edge adjustment on the OUTD falling edge, tF4.

tF4 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

tR3 adjustment reference

R/W

Setting this bit enables edge adjustment on the OUTC rising edge, tR3.

tR3 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

tF3 adjustment reference

R/W

Setting this bit enables edge adjustment on the OUTC falling edge, tF3.

tF3 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

Table 195. Register 0xFE6F—SR1 and SR2 Adjustment Reference During Synchronization

Bits

Bit Name/Function

R/W

Description

tR6 adjustment reference

R/W

Setting this bit enables edge adjustment on the SR2 rising edge, tR6.

tR6 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

tF6 adjustment reference

R/W

Setting this bit enables edge adjustment on the SR2 falling edge, tF6.

tF6 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

tR5 adjustment reference

R/W

Setting this bit enables edge adjustment on the SR1 rising edge, tR5.

tR5 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

tF5 adjustment reference

R/W

Setting this bit enables edge adjustment on the SR1 falling edge, tF5.

tF5 refers to tS or tS/2

R/W

0 = adjustment refers to tS/2.

1 = adjustment refers to tS.

All of these registers and their bits are reserved. There are no register tables available for Register 0xFE70 to Register 0xFE9F.

MANUFACTURER SPECIFIC FAULT FLAG REGISTERS

Table 196. Register 0xFEA0—Flag Register 1 and Register 0xFEA3—Latched Flag Register 1 (1 = Fault, 0 = Normal Operation)

Bits

Bit Name/Function

R/W

Description

Corresponding

Registers1

Action1

CHIP_PASSWORD_UNLOCKED

Chip password is unlocked.

N/A

None

PGOOD

At least one of the following flags has been set:

VOUT_OV_ FAULT, VOUT_UV_FAULT, IOUT_OC_FAULT,

OT_FAULT, OT_WARNING, VIN_UV_FAULT, IIN_OC_FAST_

FAULT, SR_RC_FAULT, POWER_OFF, CRC_FAULT,

SOFT_START_FILTER, or POWER_GOOD. Some of the

flags are maskable according to Register 0xFE0D.

0xFE0D and

0xFE0E

PG/ALT pin

set low

IIN_OC_FAST_FAULT

An input overcurrent fast fault is triggered.

0xFE1F

Programmable

Reserved

Reserved.

N/A

CS3_OC_FAULT

A CS3 overcurrent fault is triggered.

0xFE6A

Programmable

Reserved

Reserved.

N/A

Reserved

Reserved.

N/A

VDD_OV

VDD is above the OVLO limit. The I2C/PMBus interface

remains functional, but power conversion stops.

0xFE05

Programmable

N/A means not applicable.

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