ADP1052ACPZ-R7 datasheet(99/113 Pages) AD

99 / 113 page

Data Sheet

ADP1052

Rev. B | Page 99 of 113

Table 166. Register 0xFE52—SR1 and SR2 Modulation Settings

Bits

Bit Name/Function

R/W

Description

SR2 tR6 modulation enable

R/W

0 = no PWM modulation of the tR6 edge.

1 = PWM modulation acts on the tR6 edge.

SR2 tR6 modulation sign

R/W

0 = positive sign. Increase of PWM modulation moves tR6 to the right.

1 = negative sign. Increase of PWM modulation moves tR6 to the left.

SR2 tF6 modulation enable

R/W

0 = no PWM modulation of the tF6 edge.

1 = PWM modulation acts on the tF6 edge.

SR2 tF6 modulation sign

R/W

0 = positive sign. Increase of PWM modulation moves tF6 to the right.

1 = negative sign. Increase of PWM modulation moves tF6 to the left.

SR1 tR5 modulation enable

R/W

0 = no PWM modulation of the tR5 edge.

1 = PWM modulation acts on the tR5 edge.

SR1 tR5 modulation sign

R/W

0 = positive sign. Increase of PWM modulation moves tR5 to the right.

1 = negative sign. Increase of PWM modulation moves tR5 to the left.

SR1 tF5 modulation enable

R/W

0 = no PWM modulation of the tF5 edge.

1 = PWM modulation acts on the tF5 edge.

SR1 tF5 modulation sign

R/W

0 = positive sign. Increase of PWM modulation moves tF5 to the right.

1 = negative sign. Increase of PWM modulation moves tF5 to the left.

Table 167. Register 0xFE53—PWM Output Disable

Bits

Bit Name/Function

R/W

Description

[7:6]

Reserved

R/W

Reserved.

SR2 disable

R/W

Setting this bit disables the SR2 output.

SR1 disable

R/W

Setting this bit disables the SR1 output.

OUTD disable

R/W

Setting this bit disables the OUTD output.

OUTC disable

R/W

Setting this bit disables the OUTC output.

OUTB disable

R/W

Setting this bit disables the OUTB output.

OUTA disable

R/W

Setting this bit disables the OUTA output.

VOLT-SECOND BALANCE CONTROL REGISTERS

Table 168. Register 0xFE54—Volt-Second Balance Control General Settings

Bits

Bit Name/Function

R/W

Description

Volt-second balance enable control

R/W

Setting this bit enables volt-second balance control.

Volt-second balance control

source selection, OUTD

R/W

If this bit is set, the OUTD rising edge is selected as the start of the integration period

for volt-second balance control.

Volt-second balance control

source selection, OUTC

R/W

If this bit is set, OUTC rising edge is selected as the start of the integration period for

volt-second balance control.

Volt-second balance control

source selection, OUTB

R/W

If this bit is set, OUTB rising edge is selected as the start of the integration period for

volt-second balance control.

Volt-second balance control

source selection, OUTA

R/W

If this bit is set, OUTA rising edge is selected as the start of the integration period for

volt-second balance control.

Volt-second balance control limit

R/W

This bit sets the maximum amount of modulation from the volt-second control circuit.

0 = ±160 ns.

1 = ±80 ns.

[1:0]

Volt-second balance control gain

R/W

These bits set the gain of the volt-second balance control. The gain can be changed by

a factor of 64. When these bits are set to 00, it takes approximately 700 ms to achieve

volt-second balance. When these bits are set to 11, it takes approximately 10 ms to

achieve volt-second balance.

Bit 1

Bit 0

Volt-Second Balance Loop Gain

ADP1052ACPZ-R7 датащи(PDF) 99 Page - Analog Devices

ADP1052ACPZ-R7 датащи(HTML) 99 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL