ADP1052ACPZ-R7 datasheet(26/113 Pages) AD

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ADP1052

Data Sheet

Rev. B | Page 26 of 113

PSON SIGNAL

TON_DELAY

REG 0x60

TON_RISE

REG 0x61

HF ADC SETTLING

DEBOUNCE

REG 0xFE3D[5:4]

PGOOD DEBOUNCE

REG 0xFE0E[3:2]

VOUT

SOFT_START_FILTER FLAG

REG 0xFEA2[0]

POWER_OFF FLAG

REG 0x78[6] AND REG 0x79[6]

PG/ALT PIN

Figure 29. Soft Start Timing Diagram

If no faults are present, the PGOOD signal waits for the pro-

grammed debounce time (Register 0xFE0E[3:2]) before the

PG/ALT pin is pulled high at t4. If a fault condition occurs

during the soft start ramp (the time set by the TON_RISE

command, t1 to t2), the ADP1052 responds as programmed,

unless the flag is blanked during soft start. The user can program

which flags are active during the soft start. All flags are active at

the end of the soft start ramp (t2). See the Flag Blanking During

Soft Start section for more information.

The SR1 and SR2 outputs and volt-second balance functions

can also be disabled during the soft start ramp. For more

information, see the Synchronous Rectification section and

Volt-Second Balance Control section, respectively.

Digital Filters During Soft Start

A dedicated soft start filter is used during soft start. The soft start

filter is a pure low frequency filter with a programmable gain. The

filter is disabled at the end of the soft start routine (t2) prior to using

the general digital compensator. The soft start filter gain is pro-

grammed using Register 0xFE3D[1:0].

The soft start filter is used during the ramp time of the voltage

reference, until the VS high frequency ADC is settled. The user

can program (using Register 0xFE3D[4]) whether to add a high

frequency ADC debounce time. The high frequency ADC

debounce time is the interval from when the high frequency

ADC is settled to when the frequency filter takes action. The

debounce time can be programmed at 5 ms or 10 ms using

in use, the SOFT_START_ FILTER flag is set. It is recommended

that when a fast load transient occurs during soft start, do not

use high frequency ADC debounce time.

Software Reset

The software reset command allows the user to perform a software

reset of the ADP1052. When a 1 is written to Register 0xFE06[0],

the power supply is immediately turned off and then restarted with

a soft start following a restart delay. The restart delay time can be

programmed as 0 ms, 500 ms, 1 sec, or 2 sec (Register 0xFE07[1:0]).

If both TON_DELAY and the restart delay are programmed with

0 ms, a write to this bit has no effect.

Shutdown

When the ADP1052 is commanded to turn off, the PSON signal

clears. Depending on the setting of the OPERATION command,

the ADP1052 shuts down immediately or waits for a user specified

turn-off delay (TOFF_DELAY) prior to the shutdown action.

If the ADP1052 turns off because a fault condition occurs, the

shutdown actions are programmed by the specific fault flag

responses. See the Power Monitoring, Flags, and Fault Responses

section for more information. The PGOOD flag setting debounce

time can be programmed in Register 0xFE0E[1:0]). This debounce

time is from when the PGOOD setting condition is met to when

the PGOOD flag is set and the PG/ALT pin is pulled low.

Power-Good Signals

The ADP1052 has an open-drain, power-good pin, PG (PG/ALT,

Pin 17). When the pin is logic high, the power is good. In addition,

the ADP1052 has a power-good flag, PGOOD, which is a negation

of power good. When this flag is set, it indicates that the power is

not good. The PG/ALT pin and the PGOOD flag can be pro-

grammed to respond to the flags from the following list:

•

VIN_UV_FAULT

•

IIN_OC_FAST_FAULT

•

IOUT_OC_FAULT

•

VOUT_OV_FAULT

•

VOUT_UV_FAULT

•

OT_FAULT

•

OT_WARNING

•

SR_RC_FAULT

prevents them from setting the PGOOD flag and driving the

PG/ALT pin low; whereas Register 0xFE0E[1:0] sets the debounce

time to drive the PG/ALT pin low and set the PGOOD flag (see

Figure 30).

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