ADP1052ACPZ-R7 datasheet(19/113 Pages) AD

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Data Sheet

ADP1052

Rev. B | Page 19 of 113

set by the internal oscillator. This is the second synchroniza-

tion unlock condition, called Synchronization Unlocked

Mode 2, in which the phase shift exceeds 280 ns.

Figure 17 shows the synchronous operation. The internal

frequency, fSW_INT, is the internal free running frequency of the

ADP1052. Before the synchronization is locked, the ADP1052

runs at fSW_INT. The external frequency, fSW_EXT, is the frequency

of the external clock that the ADP1052 needs to synchronize.

After synchronization is locked, the ADP1052 runs at fSW_EXT.

The ADP1052 does not allow the switching frequency to run across

the boundaries of 97.5 kHz, 195.5 kHz, or 390.5 kHz on-the-fly.

Ensure that the external clock does not run across these boundaries;

otherwise, the internal switching frequency cannot be set within

±10% of these boundaries.

110% fSW_INT

114% fSW_INT

fSW_INT

90% fSW_INT

89% fSW_INT

UNIT

OFF

UNIT

TIME

EXTERNAL CLOCK FREQUENCY

OPERATING SWITCHING FREQUENCY

INTERNAL CLOCK FREQUENCY

fSW

Figure 17. Synchronization Operation

SYNI/FLGI

SYNI DELAY

TIME SETTING

REG 0xFE11

±3.125%

±6.25%

SYNC OPERATION

AS SLAVE DEVICE

0µs

DEBOUNCE

100µs

DEBOUNCE

FLAGIN FLAG

RESPONSE

REG 0xFE03[3:0]

SYNI MODE

FLGI MODE

SYNI ENABLE

REG 0xFE12[3]

OUTC

OUTD

OUTC IN SYNO MODE

OUTD IN SYNO MODE

DEBOUNCE TIME

REG 0xFE12[1]

SYNO ENABLE

REG 0xFE12[5:4]

POLARITY

REG 0xFE12[2]

PHASE CAPTURE

RANGE SELECTION

REG 0xFE12[6]

SYNI/FLGI

SELECTION

REG 0xFE12[0]

320ns

DEBOUNCE

Figure 18. Synchronization Configuration

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