ADP1052ACPZ-R7 datasheet(95/113 Pages) AD

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Data Sheet

ADP1052

Rev. B | Page 95 of 113

Table 155. Register 0xFE38—CS1 Threshold for Volt-Second Balance

Bits

Bit Name/Function

R/W

Description

[7:0]

CS1 threshold for

volt-second balance

R/W

This register sets the CS1 threshold to enable volt-second balance control. The volt-second balance

control function is activated only if the CS1 value is greater than this threshold value. Each LSB is

6.25 mV.

Table 156. Register 0xFE39—Nominal Modulation Value for Prebias Startup

Bits

Bit Name/Function

R/W

Description

[7:0]

Nominal modulation

value for prebias

start-up function

R/W

These bits set the nominal modulation value when the input voltage and the output voltage are in

nominal conditions. It is used to calculate the initial modulation value, based on the sensed VOUT value

and the sensed VIN value, for the prebias startup. If Register 0xFE6C[1] is cleared, the input voltage is

always regarded as the nominal input condition unless closed-loop feedforward operation is in use.

Switching Frequency Range (kHz)

Resolution Corresponding to LSB (ns)

49 to 87

97.5 to 184

195.5 to 379

390.5 to 625

Table 157. Register 0xFE3A—Constant Current Speed and SR Driver Delay

Bits

Bit Name/Function

R/W

Description

[7:6]

VS voltage change

rate during constant

current mode

R/W

These bits set the VS voltage change rate when operating in constant current mode. The basic change

rate for a 9-bit CS2 averaging speed is 1.18 mV/ms. The basic change rate for a 7-bit CS2 averaging

speed is 4.72 mV/ms. These two bits set the change rate of the output voltage when operating in

constant current mode.

For example, in a 12 V output system, if Register 0xFE1B[4] = 1 and Register 0xFE3A[7:6] = 11,

the output voltage change rate is

4.72 mV/ms × 8 × 12 = 453 mV/ms

Bit 7

Bit 6

Change Rate (mV/ms)

[5:0]

SR gate drive delay

R/W

These bits set the SR gate drive delay in steps of 5 ns. The maximum delay is 315 ns.

Table 158. Register 0xFE3B—PWM 180° Phase Shift Settings

Bits

Bit Name/Function

R/W

Description

Volt-second balance

leading edge blanking

R/W

Setting this bit means that CS1 is blanked for volt-second balance calculations at the rising edge of

those PWMs selected for volt-second balance. The blanking time is the same as for the CS1 cycle-

by-cycle current-limit setting.

Volt-second balance

50% blanking of each

phase

R/W

Setting this bit limits the sampling period for the current on CS1 to less than 50% of a half cycle.

SR2 180° phase shift

R/W

Setting this bit adds a 180° phase shift for the timing of the SR2 edges.

SR1 180° phase shift

R/W

Setting this bit adds a 180° phase shift for the timing of the SR1 edges.

OUTD 180° phase shift

R/W

Setting this bit adds a 180° phase shift for the timing of the OUTD edges.

OUTC 180° phase shift

R/W

Setting this bit adds a 180° phase shift for the timing of the OUTC edges.

OUTB 180° phase shift

R/W

Setting this bit adds a 180° phase shift for the timing of the OUTB edges.

OUTA 180° phase shift

R/W

Setting this bit adds a 180° phase shift for the timing of the OUTA edges.

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