ADP1052ACPZ-R7 datasheet(38/113 Pages) AD

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ADP1052

Data Sheet

Rev. B | Page 38 of 113

CS1 CYCLE-BY-CYCLE

CURRENT LIMIT THRESHOLD

OUTA

CS1 PIN SIGNAL

COMPARATOR

OUTPUT

CS1_OCP FLAG

tBLANKING

tDEBOUNCING

Figure 40. CS1 Cycle-by-Cycle Current-Limit Timing

When the CS1_OCP flag triggers, Register 0xFE08[6:5] and

the remainder of the switching cycle; they are reenabled at the

start of the next switching cycle. During one switching cycle, if

the rising edge of a PWM output occurs after the CS1_OCP flag

is triggered, the PWM remains enabled for the switching cycle.

To avoid current overstress of the body diode of the synchronous

rectifiers, the cycle-by-cycle current-limit actions of the SR1 and

SR2 outputs can be further programmed by Register 0xFE1E[1:0].

Program the SRx outputs in the same way as the other PWM

outputs, or program them so that when the CS1_OCP flag triggers,

the SR PWM output turns on. There is a 145 ns to 180 ns delay

(dead time) between the CS1_OCP flag being triggered and the

turning on of the SR PWM outputs. The falling edges continue

to follow the programmed value.

The cycle-by-cycle current limit is always activated regardless

of the IIN overcurrent fast protection settings. The comparator

output can be completely ignored by setting Register 0xFE1F[7].

IIN Overcurrent Fast Protection

There is an internal counter, N. N is a positive integer or zero,

with an initial value of 0. The counters work as follows:

When the CS1_OCP flag is triggered in one cycle (the CS1 OCP

comparator is triggered high), N is counted as

NCURRENT = NPREVIOUS + 2

If the CS1_OCP flag is not triggered in one cycle and NPREVIOUS is

greater than 0, then

NCURRENT = NPREVIOUS − 1

If the CS1_OCP flag is not triggered in one cycle and NPREVIOUS

equals 0, then

NCURRENT = 0

When the value of N reaches the limit specified by IIN_OC_

FAST_FAULT_LIMIT, the IIN_OC_FAST_FAULT flag is

triggered (see Figure 41).

CS1 CYCLE-BY-CYCLE CURRENT

LIMIT REFERENCE

CS1 SIGNAL

COMPARATOR

OUTPUT

IIN_OC_FAST_FAULT

FLAG REG 0xFEA0[5]

IIN_OC_FAST_FAULT

FLAG REG 0x7C[2]

IIN_OC_FAST_FAULT

FLAG REG 0xFEA[5]

Figure 41. IIN Overcurrent Fast Fault Triggering

For the single-ended topologies, such as forward converter and

buck converter, a switching cycle consists of one cycle. For the

double-ended topologies, such as full bridge converter, half

bridge converter, and push pull converter, there are two cycles

in a switching cycle. The IIN_OC_FAST_FAULT_LIMIT bits

are in Register 0xFE1A[6:4]. In Figure 41, the IIN_OC_FAST_

FAULT_LIMIT value is set to 8.

The response of the IIN_OC_FAST_FAULT flag can be

programmed in the IIN_OC_FAST_FAULT_RESPONSE bits

(Register 0xFE00[3:0]). See the Manufacturer Specific Protection

Responses section and the register settings for the action details.

Matched Cycle-by-Cycle Current Limit in a Half Bridge

Converter

For the half bridge converter, the cycle-by-cycle current-limit

feature, described previously, cannot guarantee the balance of

duty cycles between two half cycles in one switching cycle.

The imbalances of each half cycle can cause the center point

voltage of the capacitive divider to drift from VIN/2 toward either

the ground or the input voltage, VIN. This drift, in turn, can lead

to output voltage regulation failure, transformer saturation, and

doubling of the drain to source voltage (VDS) stress of the

synchronous rectifiers.

To compensate for these imbalances, matched cycle-by-cycle

current limiting is implemented in the ADP1052 by forcing

each cycle to be equalized, or matched, to the previous one.

When the matched cycle-by-cycle current limit is triggered, the

duty cycle in the following half cycle exactly matches the actual

duty cycle in the preceding half cycle. However, the cycle-by-cycle

current limit is always the highest priority to terminate the PWM

channels. For example, if one previous cycle has a duty cycle of

20% under a cycle-by-cycle current-limit condition, the following

cycle should also be matched to a duty cycle of 20%. However,

if the cycle-by-cycle current limit occurs in the following cycle and

it must terminate the PWM with a smaller duty cycle, the cycle-

by-cycle current limit takes higher priority and the duty cycle

can be a value that is smaller than 20%.

The matched cycle-by-cycle current limit is enabled by Regis-

ter 0xFE1D[6]. Register 0xFE1D[5:4] sets the PWM pairs for

the matched cycle-by-cycle current limit.

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