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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADP1052ACPZ-R7 датащи(PDF) 80 Page - Analog Devices |
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ADP1052ACPZ-R7 датащи(HTML) 80 Page - Analog Devices |
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80 / 113 page  ADP1052 Data Sheet Rev. B | Page 80 of 113 MANUFACTURER SPECIFIC EXTENDED COMMANDS DESCRIPTIONS FLAG CONFIGURATION REGISTERS Register 0xFE00 to Register 0xFE03 set the fault flag response and the resolution after the flag is cleared. Register 0xFE05[5:4] sets the VDD_OV flag response. Register 0xFE05[7:6] sets the global flag reenable delay time. Table 110. Register 0xFE00 to Register 0xFE05—Flag Response Registers Register Bits Flag Additional Settings 0xFE00 [7:4] Reserved Reserved [3:0] IIN_OC_FAST_FAULT_RESPONSE Register 0xFE08, Register 0xFE0E, Register 0xFE1A, Register 0xFE1F, Register 0xFEA0, Register 0xFEA3 0xFE01 [7:4] Extended VOUT_OV_FAULT_RESPONSE Register 0x40, Register 0x41, Register 0xFE26, Register 0xFE6B, Register 0xFE6C [3:0] CS3_OC_FAULT_RESPONSE Register 0xFE6A, Register 0xFEA0, Register 0xFEA3 0xFE02 [7:4] VIN_UV_FAULT_RESPONSE Register 0x35, Register 0x36, Register 0xFE29, Register 0xFEA1, Register 0xFEA4 [3:0] Reserved Reserved 0xFE03 [7:4] SR_RC_FAULT_RESPONSE Register 0xFE1A, Register 0xFEA1, Register 0xFEA4 [3:0] FLAGIN_RESPONSE Register 0xFE12, Register 0xFEA1, Register 0xFEA4 0xFE05 [7:6] Flag reenable delay Register 0xFE05, Register 0xFEA0, Register 0xFEA3 [5:4] VDD_OV_RESPONSE [3:0] Reserved Reserved Table 111. Register 0xFE00 to Register 0xFE02—Flag Response Register Bit Descriptions Bits Bit Name/Function R/W Description [7:6] Fault response R/W These bits specify the action when the flag is set. Bit 7 Bit 6 Flag Action 0 0 Continues operation without interruption. 0 1 Disables SR1 and SR2. 1 0 Disables all PWM outputs. 1 1 Reserved. [5:4] Action after flag is cleared R/W These bits specify the action when the flag is cleared. Bit 5 Bit 4 Action After Flag Clearing 0 0 After the reenable delay time, the PWM outputs are reenabled with a soft start. 0 1 The PWM outputs are reenabled immediately without a soft start. 1 0 A PSON signal through Register 0x01, Register 0x02, and/or the CTRL pin, is needed to reenable the PWM outputs. 1 1 Reserved. [3:2] Fault response R/W These bits specify the action when the flag is set. Bit 3 Bit 2 Flag Action 0 0 Continues operation without interruption. 0 1 Disables SR1 and SR2. 1 0 Disables all PWM outputs. 1 1 Reserved. [1:0] Action after flag is cleared R/W These bits specify the action when the flag is cleared. Bit 1 Bit 0 Action After Flag Clearing 0 0 After the reenable delay time, the PWM outputs are reenabled with a soft start. 0 1 The PWM outputs are reenabled immediately without a soft start. 1 0 A PSON signal, through Register 0x01, Register 0x02, and/or the CTRL pin, is needed to reenable the PWM outputs. 1 1 Reserved. |
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