ADP1052ACPZ-R7 datasheet(91/113 Pages) AD

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Data Sheet

ADP1052

Rev. B | Page 91 of 113

Bits

Bit Name/Function

R/W

Description

[3:2]

Light load mode and deep

light load mode hysteresis

R/W

These bits set the amount of hysteresis applied to the light load mode and deep light load mode

thresholds. The size of the LSB is affected by different speed and resolution selected in Bits[5:4].

If the 120 mV ADC range is used with 8-bit resolution, the LSB size is 120 mV/28 = 469 μV.

Bit 3

Bit 2

Hysteresis (LSB)

SR2 response to cycle-by-

cycle limit

R/W

This bit is applicable only when the SR2 output is programmed to be in complement with the

OUTA output. When this bit is set and there is a cycle-by-cycle current limit, the SR2 rising edge

is turned on when the cycle-by-cycle current limit disables the OUTA. Its falling edge still follows

the programmed value.

SR1 response to cycle-by-

cycle limit

R/W

This bit is applicable only when the SR1 output is programmed to be in complement with the

OUTB output. When this bit is set, and there is a cycle-by-cycle current limit, the SR1 rising edge

is turned on when the cycle-by-cycle current limit disables the OUTB. Its falling edge still follows

the programmed value.

Table 136. Register 0xFE1F—CS1 Cycle-by-Cycle Current-Limit Settings

Bits

Bit Name/Function

R/W

Description

CS1 cycle-by-cycle

current-limit comparator

ignored

R/W

Setting this bit causes the CS1 OCP comparator output to be ignored. The CS1_OCP internal flag

is always cleared.

[6:4]

Leading edge blanking

R/W

These bits determine the leading edge blanking time. During this time, the CS1 OCP comparator

output is ignored. This time is measured from the rising edges of OUTA, OUTB, OUTC, and OUTD

(programmable in Register 0xFE1D[3:0]).

Bit 6

Bit 5

Bit 4

Leading Edge Blanking Time (ns)

120

200

400

600

800

[3:2]

Reserved

R/W

Reserved.

[1:0]

CS1 cycle-by-cycle

current-limit

debounce time

R/W

These bits set the CS1 cycle-by-cycle current-limit debounce time. This is the minimum time that

the CS1 signal must be constantly above the CS1 cycle-by-cycle current-limit reference before the

PWM outputs are shut down. When this happens, the selected PWM outputs can be disabled for the

remainder of the switching cycle.

Bit 1

Bit 0

Debounce Time (ns)

120

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