ADP1052ACPZ-R7 datasheet(20/113 Pages) AD

20 / 113 page

ADP1052

Data Sheet

Rev. B | Page 20 of 113

Figure 19. Edge Adjustment Reference During Synchronization

To ensure a constant dead time before and after synchronization,

ment referred to tS/2 or tS. For example, the falling edge of

OUTA (tF1) is referred to the ½ × tS position, which means that

the time difference between tF1 and ½ × tS is a constant during

synchronization transition. Figure 19 shows an example of the

edge adjustment reference settings in a full bridge topology.

Synchronization as a Master Device

Use Register 0xFE12[5:4] to program the synchronization

output (SYNO) function, in which the OUTC pin (Pin 11) or

the OUTD pin (Pin 12) generates a synchronization reference

clock output. When Bit 4 is set, OUTC generates a 640 ns pulse

width clock signal that represents the internal switching frequency.

When Bit 5 is set, OUTD generates a 640 ns pulse width clock

signal that also represents the internal switching frequency.

To compensate the propagation delays in the synchronization

scheme of the ADP1052, the synchronization output signal has a

760 ns lead time before the start of the internal switching cycle.

The synchronization output signal is always available when

VDD is applied. The VDD_OV fault is the only fault condition

that suspends the synchronization output signal.

OUTPUT VOLTAGE SENSE AND ADJUSTMENT

The output voltage sense and adjustment function is used for

control, monitoring, and undervoltage protection of the remote

output voltage. VS− (Pin 1) and VS+ (Pin 2) are fully differential

inputs. The voltage sense point can be calibrated digitally to remove

any errors due to external components. This calibration can be

performed in the production environment, and the settings

stored in the EEPROM of the ADP1052 (see the Power Supply

Calibration and Trim section for more information).

For voltage monitoring, the READ_VOUT output voltage

command (Register 0x8B) is updated every 10 ms. The ADP1052

stores every ADC sample for 10 ms and then calculates the average

value at the end of the 10 ms period. Therefore, if Register 0x8B is

read at least every 10 ms, a true average value is obtained. The volt-

age information is available through the I2C/PMBus interface.

The control loop of the ADP1052 features a patented multipath

architecture. The output voltage is converted simultaneously by

two ADCs: a high accuracy ADC and a high speed ADC. To

provide a high performance and cost competitive solution, the

complete signal is reconstructed and processed in the digital

compensator.

Voltage Feedback Sensing (VS+, VS− Pins)

The output voltage feedback sense point on the power rail

requires an external resistor divider (R1 and R2 in Figure 20) to

bring the nominal differential mode signal to 1 V between the

VS+ and VS− pins (see Figure 20). This external resistor divider

is necessary because the VS ADC input range of the ADP1052 is

0 V to 1.6 V. When R1 and R2 are known, the VOUT_SCALE_

LOOP parameter can be calculated using the following

equation:

VOUT_SCALE_LOOP = R2/(R1 + R2)

In a 12 V system with resistor dividers of 11 kΩ and 1 kΩ, the

VOUT_SCALE_LOOP can be calculated as follows:

VOUT_SCALE_LOOP = 1 kΩ/(11 kΩ + 1 kΩ) = 0.08333

ADP1052ACPZ-R7 датащи(PDF) 20 Page - Analog Devices

ADP1052ACPZ-R7 датащи(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL