ADP1052ACPZ-R7 datasheet(83/113 Pages) AD

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Data Sheet

ADP1052

Rev. B | Page 83 of 113

Table 117. Register 0xFE09—Soft Start Setting of Open-Loop Operation

Bits

Bit Name/Function

R/W

Description

Open-loop operation

soft start enable

R/W

Setting this bit enables the soft start of open-loop operation.

OUTA, OUTB, OUTC, and

OUTD edges

R/W

When this bit is set, the falling edges of OUTA, OUTB, OUTC, and OUTD are always after the

rising edges in one cycle during the soft start of open-loop operation.

SR1 and SR2 edges

R/W

This bit is valid only when Bit 7 of this register is set to 1.

0 = the rising edges of SR1 and SR2 always occur after the falling edges in one cycle during

a soft start.

1 = the falling edges of SR1 and SR2 always occur after the rising edges in one cycle during

a soft start.

[4:3]

Soft start speed of open-loop

operation and open-loop

feedforward operation

R/W

When the ADP1052 is configured for open-loop operation, the falling edge of the PWM

output moves to the right in steps of 40 ns. When the ADP1052 is configured for open-

loop feedforward operation, the modulation edge of the PWM output moves from the

original position in steps of 40 ns. These bits specify how many switching cycles are

required to move the PWM outputs in 40 ns.

Bit 4

Bit 3

Open-Loop Soft Start Timing

The PWM outputs change 40 ns in one switching cycle.

The PWM outputs change 40 ns in four switching cycles.

The PWM outputs change 40 ns in 16 switching cycles.

The PWM outputs change 40 ns in 64 switching cycles.

Soft start variation for

open-loop operation

R/W

Setting this bit enables global variation during the soft start of open-loop operation.

1 = all outputs use the time variation calculated by OUTB (tF2 − tR2).

[1:0]

Reserved

R/W

Reserved.

BLANKING AND PGOOD SETTING REGISTERS

Table 118. Register 0xFE0B—Flag Blanking During Soft Start

Bits

Bit Name/Function

R/W

Description

Blank SR_RC_FAULT flag

R/W