ADP1052ACPZ-R7 datasheet(29/113 Pages) AD

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Data Sheet

ADP1052

Rev. B | Page 29 of 113

The drooping resistor follows the PMBus specifications. The

VOUT_DROOP command (Register 0x28) specifies the drooping

resistor in the range of 0 mΩ to 255 mΩ.

The CS2 (output current) averaging speed dictates how quickly

the output current is sensed for generating the digital voltage

reference. Set Register 0xFE1E[7:6] to change the output current

update speed from 82 μs to 656 μs. An output current update of

82 µs is recommended.

VDD AND VCORE

When the voltage of the VDD pin is applied (VDD), there is a

delay before the device can regulate the power supply. When VDD

rises above the power-on reset and UVLO levels, it takes ~20 μs for

the VCORE pin (Pin 18) to reach its operational point of 2.6 V.

The EEPROM contents are then downloaded to the registers. The

download takes approximately an additional 120 μs. After the

EEPROM contents are downloaded, the ADP1052 is ready for

operation; however, it takes a maximum of 52 ms for the ADP1052

to complete initialization of the address after a power-on reset.

Therefore, it is recommended that the master device access the

ADP1052 at least 52 ms after power-on reset.

If the ADP1052 is programmed to power up at this time, the soft

start ramp begins. Otherwise, the device waits for a PSON

signal, programmed in Register 0x01 and Register 0x02.

To minimize trace length, the proper amount of decoupling

capacitance must be placed between the VDD pin (Pin 19) and the

AGND pin (Pin 20), as close as possible to the device. The same

requirement applies to the VCORE pin (Pin 18). It is recom-

mended that the VCORE pin not be used as a reference or to

generate other logic levels using resistive dividers.

CHIP PASSWORD

On power-up, some registers in the ADP1052 are locked and

protected from being written to or read from. When the chip is

locked, the following commands and all read-only registers are

accessible:

•

OPERATION

•

ON_OFF_CONFIG

•

CLEAR_FAULTS

•

WRITE_PROTECT

•

RESTORE_DEFAULT_ALL

•

VOUT_COMMAND

•

VOUT_TRIM

•

VOUT_CAL_OFFSET

Unlock the Chip Password

To unlock the chip password, perform two consecutive writes

with the correct password (default value = 0xFFFF) and use the

CHIP_PASSWORD command (Register 0xD7). Between the two

write actions, any read or write action to another register in this

device interrupts the unlocking of the chip password. The

CHIP_PASSWORD_UNLOCKED flag (Register 0xFEA0[7]) is

set to indicate that the chip password is unlocked for access.

Lock the Chip Password

To lock the chip password, use the CHIP_PASSWORD command

(Register 0xD7) to write any value other than the correct password.

The CHIP_PASSWORD_UNLOCKED flag (Register 0xFEA0[7])

is then cleared to indicate that the chip password is locked from

access.

Change the Chip Password

To change the chip password, first write the old password, using the

CHIP_PASSWORD command (Register 0xD7). Next, write the

new password, using the same command. The chip password is

changed to the new password. If the chip password is to be changed

permanently, the register contents must be saved in the EEPROM

after the chip password is changed. If the correct chip password is

lost, the RESTORE_DEFAULT_ALL command (Register 0x12)

restores the factory default settings. In this case, all the user settings

reset.

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