ADP1052ACPZ-R7 datasheet(18/113 Pages) AD

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ADP1052

Data Sheet

Rev. B | Page 18 of 113

To achieve normal operation of light load mode, keep in mind

the following:

In a hard switched, full bridge topology having the same power

stage as shown in Figure 12, if QA to QD are driven by OUTA

to OUTD separately, program the SR1 output in complement

with OUTB and OUTC in normal mode, and program the SR2

output in complement with OUTA and OUTD (as shown

in Figure 16). In this case, the OUTA to OUTD outputs are all

modulated.

In a zero-voltage-switched full bridge topology having the same

power stage shown in Figure 12 and the PWM settings shown

in Figure 13, SR1 is in complement with OUTC and SR2 is in

complement with OUTA in normal mode. In light load mode,

SR1 is in phase with OUTA, and SR2 is in phase with OUTC.

If using the hard switched full bridge, half bridge, and push pull

topologies and the primary switches are controlled by OUTA

and OUTB only, SR1 is in complement with OUTB, and SR2 is

in complement with OUTA in normal mode. Then, in the light

load mode, SR1 is in phase with OUTA, and SR2 is in phase

with OUTB.

When the CS2 current drops across the deep light load mode

threshold programmed by Register 0xFE1B[3:0], all PWM

channels can be disabled by Register 0xFE1C[5:0]. This allows use

of the ADP1052 in interleaved topologies, incorporating the

automatic phase shedding function in light load mode.

In both light load mode and deep light load mode, the CS2

averaging speed for the threshold can be set from 41 μs to 328 μs

in four discrete steps, using Register 0xFE1E[5:4]. Set the

hysteresis in Register 0xFE1E[3:2].

The light load mode digital compensator is also used during light

load mode and deep light load mode.

FREQUENCY SYNCHRONIZATION

The frequency synchronizing function of the ADP1052 includes

the synchronization input (SYNI function of SYNI/FLGI) as a

slave device and the synchronization output (SYNO, using the

OUTC or OUTD pin) as a master device.

Synchronization as a Slave Device

The ADP1052 can be programmed to take the SYNI/FLGI pin

signal as the reference to synchronize the internal programmed

PWM clock with an external clock. Note that where the SYNI

or the FLGI function only of the SYNI/FLGI pin is referenced,

the pin name reflects the relevant function only (see the Pin

Configuration and Function Descriptions section for full pin

mnemonics and descriptions).

The frequency capture range requirement is for the period of

the external clock that is applied at the SYNI pin to be 90% to

110% of the period of the internal programmed PWM clock. The

minimum pulse width of the SYNI signal is 360 ns. From the

rising edge of the SYNI signal to the start of the internal clock

cycle, there is a 760 ns propagation delay. Additional delay time

is programmed, using Register 0xFE11, to realize interleaving

control with different controllers.

To achieve a smooth synchronization transition between asynchro-

nous operation and synchronous operation, there is a phase capture

range bit for synchronization in Register 0xFE12[6] for capturing

the phase of the external clock signal. The ADP1052 detects the

phase shift between the external clock signal and the internal clock

signal when synchronization is enabled. When the phase shift

falls within the phase capture range, synchronization begins.

The ADP1052 synchronizes to the external clock frequency as

follows:

1. Bit 3 and Bit 0 in Register 0xFE12 enable the synchronization

function; the ADP1052 starts to detect the period of the

external clock signal applied at the SYNI/FLGI pin.

2. If all the periods of the consecutive 64 most recent cycles of

the external clocks fall within 90% to 110% of the internal

switching clock period, the ADP1052 uses the latest current

cycle as the synchronization reference, and the period of the

external clock is identified. This interval is t2 or t4, as shown

in Figure 17. Otherwise, the ADP1052 discards this cycle

and looks for the next cycle (frequency capture mode).

3. After the external clock period is determined, the

ADP1052 detects the phase shift between the external

clock (plus the delay time set by Register 0xFE11) and the

internal PWM signal. If the phase shift is within the phase

capture range, the internal and external clocks are

synchronized (phase capture mode).

4. At this point, the PWM clock is synchronized with the

external clock. Cycle-by-cycle synchronization starts.

5. If the external clock signal is lost at any time, or if the

period exceeds the minimum limit (89% of the internal

programmed frequency) or the maximum limit (114% of

the internal programmed frequency), the ADP1052 takes the

last valid external clock signal as the synchronization

reference source. At the same time, the phase shift between

the synchronization reference and the internal clock is

detected. When the phase shift falls within the phase

capture range, the PWM clock returns to the internal clock

set by the internal oscillator. This interval is t1 or t3, as

shown in Figure 17.

This is the first synchronization unlock condition, called

Synchronization Unlocked Mode 1, in which the switching

frequency is out of range (range is 89% to approximately

114% of the internal programmed frequency).

6. If the period of the external SYNI signal changes significantly

(for example, if the period difference between contiguous

cycles exceeds 280 ns), the ADP1052 adopts the last valid

external clock signal for the synchronization reference

source. At the same time, the phase shift between the

synchronization reference and the internal clock is

detected. When the phase shift falls within the phase

capture range, the PWM clock returns to the internal clock

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