ADP1052ACPZ-R7 datasheet(17/113 Pages) AD

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Data Sheet

ADP1052

Rev. B | Page 17 of 113

is disabled, the edges are always located between t0 and tS. When

the 180° phase shift is enabled, the edges are located between tS/2

and 3tS/2.

Use the 180° phase shift function to extend the maximum duty

cycle in a multiphase, interleaved converter. Figure 15 shows

a dual-phase, interleaved buck converter. The OUTC and OUTD

PWM outputs are programmed as a 180° phase shift with the

OUTA and OUTB PWM outputs.

Use the phase shedding function for light load efficiency improve-

ment. See the Light Load Mode and Deep Light Load Mode section

for more information. The ADP1052 GUI is recommended for

evaluating this feature.

LOAD

INPUT

DRIVER

Figure 15. Dual-Phase Interleaved Buck Converter Controlled by the

ADP1052

ADAPTIVE DEAD TIME COMPENSATION (ADTC)

The ADTC registers (Register 0xFE5A to Register 0xFE60 and

be adapted on the fly. The ADP1052 uses the ADTC function only

when the CS1 current value (which represents the input current)

falls below the ADTC threshold (programmed in Register 0xFE5A,

see Table 174). The ADP1052 GUI allows the user to program the

dead time values easily, and it is recommended to use the GUI for

this purpose.

Before configuring the ADTC, its threshold must be programmed.

Each individual PWM rising and falling edge (tRX and tFX) can

then be programmed (Register 0xFE5B to Register 0xFE60) to

have a specific dead time offset at a CS1 current of 0 A.

This offset can be positive or negative and is relative to the nominal

edge position. When the CS1 current is between 0 A and the

ADTC threshold, the amount of dead time is linearly adjusted in

steps of 5 ns.

The averaging period of the CS1 current and the speed of

the dead time adjustment can also be programmed in Regis-

ter 0xFE66 to accommodate faster or slower adjustment.

For example, if the ADTC threshold is set to 0.8 A, tR1 has a

nominal rising edge of 100 ns. If the ADTC offset setting for tR1

is 100 ns at a CS1 current of 0 A, tR1 moves to 200 ns when the CS1

current is 0 A and to 150 ns when the CS1 current is 0.4 A.

Similarly, the ADTC can be applied in the negative direction.

LIGHT LOAD MODE AND DEEP LIGHT LOAD MODE

To facilitate efficiency over the load range, the following three

operation modes can be configured in the ADP1052, according

to the voltage on the CS2± pins (to delineate this voltage from

the pins, this data sheet refers to this voltage as the CS2 current,

or sometimes the CS2 threshold):

•

Normal mode. In normal mode, the SR PWM outputs are

in complement with the primary PWM outputs.

•

Light load mode. The SR PWM outputs work, but they are

in phase with the primary PWMs.

•

Deep light load mode. All PWM outputs can be disabled.

Figure 16 shows the operation timing of a hard switched, full

bridge converter. When the CS2 current (output current) drops

across the light load mode threshold programmed by

from complementary mode (normal mode) to in-phase mode

(light load mode), as shown in Figure 16.

NORMAL MODE

LIGHT LOAD MODE

DEEP LIGHT LOAD

MODE

OUTA, OUTD

OUTB, OUTC

SR1, I_SR1

SR2, I_SR2

Vp_T1, Ip_T2

OUTA, OUTD

OUTB, OUTC

SR1, I_SR1

SR2, I_SR1

Vp_T1, Ip_T2

OUTA, OUTD

NOTES

1Vp_T IS THE TRANSFORMER PRIMARY VOLTAGE.

2Ip_T IS THE TRANSFORMER PRIMARY CURRENT.

OUTB, OUTC

SR1, I_SR1

SR2, I_SR2

Vp_T1, Ip_T2

Figure 16. Light Load Mode and Deep Light Load Mode

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