ADP1052ACPZ-R7 datasheet(25/113 Pages) AD

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Data Sheet

ADP1052

Rev. B | Page 25 of 113

The ADC samples at a frequency of 1.56 MHz, and the reading

is averaged in an asynchronous fashion. This reading is used to

determine actions on faults, such as the IOUT OC fault, with an

average rate of 82 μs (seven bits) or 328 μs (nine bits), which is

set by Register 0xFE1B[4]. The ADP1052 also reports an output

current reading in the READ_IOUT command (Register 0x8C),

with an average rate of 10 ms, 63 ms, 126 ms, 252 ms, or 504 ms

set by Register 0xFE65[2:0].

Various limits and response actions can be set for CS2, such as the

IOUT_OC_FAULT_LIMIT command (Register 0x46) and the

IOUT_OC_FAULT_RESPONSE (Register 0x47) command.

These limits and responses are described in the PMBus Command

Set and Current Sense and Limit Setting Registers sections.

SOFT START AND SHUTDOWN

On/Off Control

The OPERATION command (Register 0x01) and the

ON_OFF_ CONFIG command (Register 0x02) control the

power-on and power-off behaviors of the ADP1052. The

OPERATION command turns the ADP1052 on and off in

conjunction with input from the CTRL pin (Pin 16). The

combination of the CTRL pin input and serial bus commands

required to turn the ADP1052 on and off is configured by the

ON_OFF_CONFIG command. When commanding the

ADP1052 to turn on, the power supply on (PSON) signal is

enabled, and the ADP1052 follows the soft start procedure to

begin the power conversion.

Soft Start

After VDD power-up and initialization, when the ADP1052 is

commanded to turn on, the PSON signal is enabled. The controller

waits for a user specified turn-on delay (TON_DELAY, Regis-

ter 0x60) before initiating this output voltage soft start ramp.

The soft start is then performed by actively regulating the output

voltage and digitally ramping up the target voltage to the com-

manded voltage setpoint. The rise time of the voltage ramp is

programmed, using the TON_RISE command (Register 0x61), to

minimize the inrush currents associated with the start-up voltage

ramp. A nonzero prebiased voltage results in a longer turn on delay

and shorter rise time.

When the user turns on the power supply, the following soft start

procedure is initiated (see Figure 29):

At t = t0, the PSON signal is enabled by a combination

of the OPERATION command, the ON_OFF_CONFIG

command, and/or the CTRL pin. The ADP1052 verifies that

the initial flags indicate no abnormalities.

The ADP1052 waits for the programmed TON_DELAY time

to ramp up the power stage voltage at t1. The soft start filter

gain (set by Register 0xFE3D[1:0]) is used for closed-loop

control.

The soft start begins to ramp up the internal reference. The

soft start ramp time is programmed using the TON_RISE

command.

At t2, the soft start ramp reaches the output voltage setpoint.

The high frequency ADC starts to settle.

Additional high frequency ADC settling debounce time can

be programmed using Register 0xFE3D[5:4]. If the debounce

time is used, the high frequency ADC is activated at t3. The

period between t2 and t3 is the high frequency ADC settling

debounce time. At t3, the control loop is switched from the

soft start filter to the normal filter.

CTRL

REG 0x02[1]

REG 0x01[7:6]

REG 0x02[0]

OFF

IMMEDIATE

OFF

DELAY OFF

OPERATION

(SOFTWARE)

REG 0x01[5:4]

REG 0x02[4:2]

ALWAYS ON

ON/OFF

OPERATION

VOUT COMMAND

VOUT MARGIN LOW

VOUT MARGIN HIGH

IMMEDIATE

OFF

DELAY OFF

Figure 28. On/Off Control Diagram

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