ADP1052ACPZ-R7 datasheet(101/113 Pages) AD

101 / 113 page

Data Sheet

ADP1052

Rev. B | Page 101 of 113

DUTY CYCLE READING SETTING REGISTERS

Table 172. Register 0xFE58—Duty Cycle Reading Settings

Bits

Bit Name/Function

R/W

Description

[7:6]

Reserved

R/W

Reserved.

OUTD duty cycle reporting

R/W

1 = READ_DUTY_CYCLE reports OUTD duty cycle value.

OUTC duty cycle reporting

R/W

1 = READ_DUTY_CYCLE reports OUTC duty cycle value.

OUTB duty cycle reporting

R/W

1 = READ_DUTY_CYCLE reports OUTB duty cycle value.

OUTA duty cycle reporting

R/W

1 = READ_DUTY_CYCLE reports OUTA duty cycle value.

Duty cycle reporting for

phase-shifted topology

R/W

Setting this bit enables duty cycle reporting for phase-shifted full bridge topology. The duty cycle

value represents the overlapping of OUTA and OUTD in the phase-shifted full bridge topology.

Polarity setting for input

voltage compensation

R/W

Setting this bit applies an offset on the input voltage reading, READ_VIN, based on the reading of

the input current, READ_IIN. The compensation multiplier is set in Register 0xFE59. It is used to

compensate the voltage drop caused by the current conduction.

0 = positive polarity compensation.

1 = negative polarity compensation.

Table 173. Register 0xFE59—Input Voltage Compensation Multiplier

Bits

Bit Name/Function

R/W

Description

[7:0]

Input voltage compensation

multiplier

R/W

These bits specify the multiplier, N, for the input voltage compensation coefficient. The

compensation equation is N × (Register 0xFEA7[15:4] value) ÷ 211, and the result is added to

ADAPTIVE DEAD TIME COMPENSATION REGISTERS

Table 174. Register 0xFE5A—Adaptive Dead Time Compensation Threshold

Bits

Bit Name/Function

R/W

Description

[7:0]

Adaptive dead time

compensation

threshold

R/W

This register sets the adaptive dead time compensation threshold. The 8-bit number is compared to

the 8 MSBs of the CS1 value register (Register 0xFEA7). When the CS1 current falls below this threshold,

the edges of the PWM signals are affected as a linear function of the CS1 current, as programmed in

compensation function is disabled.

Table 175. Register 0xFE5B—OUTA Dead Time

Bits

Bit Name/Function

R/W

Description

tR1 polarity

R/W

0 = positive polarity; 1 = negative polarity.

[6:4]

tR1 offset multiplier

R/W

This value multiplies the step size specified by Register 0xFE66[2:0] to determine the tR1 offset from

nominal timing at 0 A input current.

Bit 6

Bit 5

Bit 4

Multiplier

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