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VSC7440 датащи(PDF) 132 Page - Microsemi Corporation

номер детали VSC7440
подробное описание детали  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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производитель  MICROSEMI [Microsemi Corporation]
домашняя страница  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

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Functional Descriptions
VMDS-10492 VSC7440 Datasheet Revision 4.2
115
in Table 73, page 114, only untagged frames or VLAN-tagged frames where the outer VLAN tag’s TPID is
not disabled are considered.
The basic classifier can recognize VRAP frames and redirect them to the CPU. This is a proprietary
frame format, which is used for reading and writing switch configuration registers through Ethernet
frames. For more information, see VRAP Engine, page 289.
The VRAP filter in the classifier performs three checks in order to determine whether a frame is a VRAP
frame:
1.
VLAN check. The filter can be either VLAN unaware or VLAN aware
(ANA_CL::VRAP_CFG.VRAP_VLAN_AWARE_ENA). If VLAN unaware, VRAP frames must be
untagged. If VLAN aware, VRAP frames must be VLAN tagged and the frame’s VID must match a
configured value (ANA_CL::VRAP_CFG.VRAP_VID). Double VLAN tagged frames always fail this
check.
2.
EtherType and EPID check. The EtherType must be 0x8880 and the EPID (bytes 0 and 1 after the
EtherType) must be 0x0004.
3.
VRAP header check. The VRAP header (bytes 0, 1, 2, and 3 after the EPID) must match a 32-bit
configured value (ANA_CL::VRAP_HDR_DATA) where any bits can be don’t cared by a mask
(ANA_CL::VRAP_HDR_MASK).
If all three checks are fulfilled, frames are redirected to CPU extraction queue
ANA_CL::CPU_PROTO_QU_CFG.CPU_VRAP_QU. The VRAP filter is enabled in
ANA_CL:PORT:CAPTURE_CFG.CPU_VRAP_REDIR_ENA.
3.16.1.9 Logical Port Mapping
The basic classifier works on the physical port number given by the interface where the frame was
received. Other device blocks work on a logical port number that defines the link aggregation instance
rather than the physical port. The logical port number is defined in
ANA_CL:PORT:PORT_ID_CFG.LPORT_NUM. It is, for instance, used for learning and forwarding in
ANA_L2.
3.16.2
VCAP CLM Processing
Each frame is matched six times against entries in the VCAP CLM. The matching is done in serial
implying results from one match can influence the keys used in the next match.
The VCAP CLM returns an action for each enabled VCAP CLM lookup. If the lookup matches an entry in
VCAP CLM, the associated action is returned. If an entry is not matched, a per-port default action is
returned. There is no difference between an action from a match and a default action.
3.16.2.1 VCAP CLM Port Configuration and Key Selection
This section provides information about special port configurations that control the key generation for
VCAP CLM.
The following table lists the registers associated with port configuration for VCAP CLM.
VCAP CLM is looked up if the lookup is enabled by the port configuration
(ADV_CL_CFG.LOOKUP_ENA) or if the previous VCAP CLM lookup has returned a key type for the next
lookup through VCAP CLM action NXT_KEY_TYPE. However, if the previous lookup returns
NXT_KEY_TYPE = CLMS_DONE, then no further lookups are done, even if the port has enabled the
lookup.
Table 74 •
Port Configuration of VCAP CLM
Register
Description
Replication
ANA_CL:PORT:ADV_CL_CFG
Configuration of the key selection for the VCAP CLM.
Enables VCAP CLM lookups.
Per port per lookup
ANA_CL::CLM_MISC_CTRL
Force lookup in VCAP CLM for looped frames or frames
where processing is terminated by a pipeline point.
None



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