VSC7440 datasheet(46/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

OB supply options (1.0 V or 1.2 V) for optimized drive strength

OB slew rate control

•

Loopbacks for system diagnostics

3.8

Copper Transceivers

This section describes the high-level functionality and operation of two built-in copper transceivers. The

integration is kept as close to multichip PHY and switch designs as possible. This allows a fast path for

software already running in a similar distributed design while still benefiting from the cost savings

provided by the integration.

3.8.1

The registers of the integrated transceivers are not placed in the memory map of the switch, but are

attached instead to the built-in MII management controller 0 of the device. As a result, PHY registers are

accessed indirectly through the switch registers. For more information, see MII Management Controller,

page 350.

In addition to providing the IEEE 802.3 specified 16 MII Standard Set registers, the PHYs contain an

extended set of registers that provide additional functionality. The devices support the following types of

registers:

•

IEEE Clause 22 device registers with addresses from 0 to 31

•

Two pages of extended registers with addresses from 16E1 through 30E1 and 16E2 through 30E2

•

General-purpose registers with addresses from 0G to 30G

•

IEEE Clause 45 device registers accessible through the Clause 22 registers 13 and 14 to support

IEEE 802.3az Energy Efficient Ethernet registers

The memory mapping is controlled through PHY_MEMORY_PAGE_ACCESS::PAGE_ACCESS_CFG.

The following illustration shows the relationship between the device registers and their address spaces.

Figure 9 •

3.8.1.1

Broadcast Write

The PHYs can be configured to accept MII PHY register write operations, regardless of the destination

address of these writes. This is enabled in PHY_CTRL_STAT_EXT::BROADCAST_WRITE_ENA. This

enabling allows similar configurations to be sent quickly to multiple PHYs without having to do repeated

MII PHY write operations. This feature applies only to writes; MII PHY register read operations are still

interpreted with “correct” address.

3.8.1.2

The PHY can be reset through software, enabled in PHY_CTRL::SOFTWARE_RESET_ENA. Enabling

this field initiates a software reset of the PHY. Fields that are not described as sticky are returned to their

IEEE 802.3

Standard

Registers

Main Registers

0x0000

Extended

Registers 1

0x0001

16E1

17E1

18E1

19E1

30E1

Extended

Registers 2

0x0002

16E2

17E2

18E2

19E2

30E2

Extended

Registers 3

0x0003

16E3

17E3

18E3

19E3

30E3

General Purpose

Registers

0x0010

15G

16G

17G

18G

19G

30G

Clause 45

Registers

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