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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

113

The basic classified tag information can be overwritten by more intelligent decisions made in the VCAP

CLM.

3.16.1.7 Link Aggregation Code Generation

This section provides information about the functions in link aggregation code generation.

The following table lists the registers associated with aggregation code generation.

The classifier generates a link aggregation code, which is used in the analyzer when selecting to which

port in a link aggregation group a frame is forwarded.

The following contributions to the link aggregation code are configured in the AGGR_CFG register.

•

Destination MAC address—use the 48 bits of the DMAC.

•

Reversed destination MAC address—use the 48 bits of the DMAC in reverse order (bit 47 becomes

bit 0, bit 46 becomes bit 1, and so on).

•

Source MAC address—use the lower 48 bits of the SMAC.

•

IPv6 flow label—use the 20 bits of the flow label.

•

Source and destination IP addresses for IPv4 and IPv6 frames —use all bits of both the SIP and DIP.

•

TCP/UDP source and destination ports for IPv4 and IPv6 frames use the 16 bits of both the SPORT

and DPORT.

•

Random aggregation code—use a 4-bit pseudo-random number.

All contributions that are enabled are 4-bit XOR’ed, and the resulting code is used by the Layer 2

forwarding function (ANA_AC) to select 1 out of 16 link aggregation port masks. The 16 link aggregation

port masks are configured in ANA_AC:AGGR. For more information see Aggregation Group Port

Selection, page 188.

If AGGR_CFG.AGGR_USE_VSTAX_AC_ENA is enabled and the frame has a VStaX header, all other

contributions to link aggregation code calculation are ignored, and the AC field of the VStaX-header is

used directly. Otherwise, link aggregation code generation operates as previously described.

Note that AGGR_CFG.AGGR_DMAC_REVERSED_ENA and AGGR_CFG.AGGR_DMAC_ENA are

independent. If both bits are enabled, the frame’s DMAC contributes both normally and reversed in the

link aggregation code calculation.

3.16.1.8 CPU Forwarding Determination

The following table lists the registers associated with CPU forwarding in the basic classifier.

Table 71 •

Aggregation Code Generation Registers

Description

Replication

ANA_CL::AGGR_CFG

Configures use of Layer 2 through Layer 4 flow information

for link aggregation code generation.

Common

Table 72 •

CPU Forwarding Registers

Description

Replication

ANA_CL:PORT:CAPTURE_CFG

Enables CPU forwarding for various frame types.

Configures valid TPIDs for CPU forwarding.

Per port

ANA_CL:PORT:CAPTURE_BPDU_CFG

Enables CPU forwarding per BPDU address

Per port

ANA_CL:PORT:CAPTURE_GXRP_CFG

Enables CPU forwarding per GxRP address

Per port

ANA_CL:PORT:CAPTURE_Y1731_AG_CFG

Enables CPU forwarding per Y.1731/IEEE802.1ag

address

Per port

ANA_CL::CPU_PROTO_QU_CFG

CPU extraction queues for various frame types

None

ANA_CL::CPU_8021_QU_CFG

CPU extraction queues for BPDU, GARP, and

Y.1731/IEEE802.1ag addresses

None

ANA_CL::VRAP_CFG

VLAN configuration of VRAP filter

None

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