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VSC7440 датащи(PDF) 84 Page - Microsemi Corporation

номер детали VSC7440
подробное описание детали  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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производитель  MICROSEMI [Microsemi Corporation]
домашняя страница  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 датащи(HTML) 84 Page - Microsemi Corporation

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Functional Descriptions
VMDS-10492 VSC7440 Datasheet Revision 4.2
67
Write action to cache: VCAP_ACTION_DAT[2][31:0] = zero-extend(action[66:61]),
VCAP_ACTION_DAT[1][31:0] = action[60:29], VCAP_ACTION_DAT[0][31:3] = action[28:0], and
VCAP_ACTION_DAT[0][2:0] = 4, because type-group field for the X4 CLM action at address offset 0 is
0b100.
Write cache to VCAP memory by setting VCAP_UPDATE_CTRL = (4|(1412<<3)).
Once VCAP_UPDATE_CTRL.UPDATE_SHOT is cleared, then the rule has been completely written to
memory and will be able to match TRI_VID keys applied to the CLM1 VCAP.
3.12.4.2 Writing an ES0 Rule
This example shows how to write an ES0 rule, consisting of ISDX entry and ES0 action, to the VCAP
ES0.
The ES0 is not part of any resource sharing so it owns the entire address range 0-511. In this example,
the rule is written to address 215.
Software is expected to track memory usage so that it only writes to VCAP memory which does not
already contain active rules.
The ISDX entry is 30 bits wide and the action is 285 bits wide. For information about how to build a ISDX
entry and ES0 action, see VCAP_ES0 Lookup, page 247.
3.12.4.2.1 Writing a Rule to ES0
Software is not allowed to modify the cache while VCAP operation is ongoing. Always check if
VCAP_UPDATE_CTRL.UPDATE_SHOT is cleared before starting to modify the cache. If a previous
operation is still ongoing, then wait for the UPDATE_SHOT to clear.
When a new rule is started, first clear cache’s entry, action, and counter by setting
VCAP_UPDATE_CTRL.CLEAR_CACHE = 1.
Write entry data to cache: VCAP_ENTRY_DAT[0][31:0] = zero-extend(entry data[29:0]).
Write entry mask to cache: VCAP_MASK_DAT[0][31:0] = zero-extend(entry mask[29:0]).
Write action to cache: VCAP_ACTION_DAT[8][31:0] = zero-extend(action[284:256]),
VCAP_ACTION_DAT[7][31:0] = action[255:224], VCAP_ACTION_DAT[6][31:0] = action[223:192],
VCAP_ACTION_DAT[5][31:0] = action[191:160], VCAP_ACTION_DAT[4][31:0] = action[159:128],
VCAP_ACTION_DAT[3][31:0] = action[127:96], VCAP_ACTION_DAT[2][31:0] = action[95:64],
VCAP_ACTION_DAT[1][31:0] = action[63:32], and VCAP_ACTION_DAT[0][31:0] = action[31:0].
Enable the rule by setting VCAP_RULE_ENA = 1.
Write cache to VCAP memory by setting VCAP_UPDATE_CTRL = (4|(215<<3)).
After VCAP_UPDATE_CTRL.UPDATE_SHOT is cleared, the rule is completely written to memory and
will be able to match ISDX keys applied to the VCAP ES0.
3.13
Pipeline Points
This section describes the use of pipeline points in the processing flow through the switch core. A
pipeline point defines a specific position in the processing flow where frames can be injected, extracted,
discarded, or looped. These actions are special, because they define either a starting point (inject) or an
ending point (extract, discard, loop) in the processing flow. A starting point identifies the point in the
processing flow where the processing of the frame begins. Similarly, an ending point identifies the point
in the processing flow where the processing of the frame ends.
Frames subject to one of the actions injection, extraction, discarding, or looping, are assigned the
associated pipeline point as well as a pipeline action defining what caused the pipeline point to be
triggered. All frames are physically passed through all blocks of the processing flow, but each frame's
pipeline point control determines whether it is actively processed in a given block or passed transparently
to the next block; this includes which counters and policers are active.
The logical processing flow for a frame is shown in the following illustration. As an example of how the
pipeline points affect the processing flow, consider a frame being discarded by the VLAN acceptance



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