VSC7440 datasheet(64/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

PCS_10GBASE_R::RX_FSET_FIFO_STAT can be used to know how many ordered sets are captured

and FIFO full status.

3.10.2.3 Signal Detect

The PCS can be enabled to react to loss of signal through signal detect

(PCS_10GBASE_R::PCS_SD_CFG.SD_ENA). Upon loss of signal, the PCS Rx state machine is

restarted, and frame reception stops. If signal detect is disabled, no action is taken upon loss of signal.

The polarity of signal detect is configurable by PCS_10GBASE_R::PCS_SD_CFG.SD_POL, where value

of this bit indicates the active Signal Detect state of the selected input line.

The source of signal detect is selected in PCS_10GBASE_R::PCS_SD_CFG.SD_SEL to either the

SERDES PMA or the PMD receiver. If the SERDES PMA is used as source, the SERDES macro

provides the signal detect. If the PMD receiver is used as source, signal detect is sampled externally

through one of the GPIO pins on the device. For more information about the configuration of the GPIOs

and signal detect, see Parallel Signal Detect, page 354.

3.10.2.4 Tx Loopback

For debug purposes, there is a loopback path defined within all PCS blocks that loops back Tx data path

into the Rx data path. This is enabled through PCS_10GBASE_R::PCS_CFG.PMA_LOOPBACK_ENA

for PCS SFI.

3.10.2.5 Test Patterns

The following table lists the registers associated with configuring SFI PCS

Table 26 •

DEV10G BASE-R PCS Test Pattern Configuration Registers Overview

Target::Register.Field

Description

Replication

PCS_10GBASE_R::PCS_CFG.TX_TEST_

MODE

Enables test pattern mode in SFI PCS transmitter.

Per PCS

PCS_10GBASE_R::PCS_CFG.TX_TEST_

MODE

Enables test pattern mode in SFI PCS receiver.

Per PCS

PCS_10GBASE_R::TEST_CFG

Test pattern configuration register when test mode is

enabled for SFI PCS

Per PCS

PCS_10GBASE_R::TX_SEEDA_MSB.TX

_SEEDA_MSB

Most significant 26 bits of seed A used to initialize SFI

PCS scrambler in test mode.

Per PCS

PCS_10GBASE_R::TX_SEEDA_LSB.TX_

SEEDA_LSB

Least significant 32 bits of seed A used to initialize SFI

PCS scrambler in test mode.

Per PCS

PCS_10GBASE_R::TX_SEEDB_MSB.TX

_SEEDB_MSB

Most significant 26 bits of seed B used to initialize SFI

PCS scrambler in test mode.

Per PCS

PCS_10GBASE_R::TX_SEEDB_LSB.TX_

SEEDB_LSB

Least significant 32 bits of seed B used to initialize SFI

PCS scrambler in test mode.

Per PCS

PCS_10GBASE_R::TX_DATAPAT_MSB.T

X_DATAPAT_MSB

Most significant 32 bits of 64-bit data pattern used in

pseudo-random and user-defined test pattern mode for

transmitter of SFI PCS.

Per PCS

PCS_10GBASE_R::TX_DATAPAT_LSB.T

X_DATAPAT_LSB

Least significant 32 bits of 64-bit data pattern used in

pseudo-random and user-defined test pattern mode for

transmitter of SFI PCS.

Per PCS

PCS_10GBASE_R::RX_DATAPAT_MSB.

RX_DATAPAT_MSB

Most significant 32 bits of 64-bit data pattern used in

pseudo-random and user-defined test pattern mode for

receiver of SFI PCS.

Per PCS

PCS_10GBASE_R::RX_DATAPAT_LSB.R

X_DATAPAT_LSB

Least significant 32 bits of 64-bit data pattern used in

pseudo-random and user-defined test pattern mode for

receiver of SFI PCS.

Per PCS

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