VSC7440 datasheet(61/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

3.10.1.1 Clock and Reset

There is a number of synchronous resets in the DEV10G port module. All of the resets can be set and

cleared simultaneously. By default, all blocks are in the reset state (reset active). The following tables

lists all available resets.

When changing the MAC configuration, the port must go through a reset cycle. This is done by writing

the register DEV10G::DEV_RST_CTRL twice. On the first write, all reset bits must be set to active (0x1).

On the second write, reset bits are cleared (0x0). Non-reset bits in DEV10G::DEV_RST_CTRL must

keep their value for both writes.

3.10.1.2 Interrupts

The following table lists the five interrupt sources defined for DEV10G port module. For more information

about general interrupt handling, see Interrupt Controller, page 364.

All the sticky events in SFI PCS can generate an interrupt if their corresponding interrupt mask is set to 1.

The following table lists the interrupt registers that are used for interrupt generation if corresponding

event bit is set from 10GBASE-R PCS (or SFI PCS).

Table 19 •

DEV10G Reset Registers Overview

Target::Register.Field

Description

DEV10G::DEV_RST_CTRL.MAC_RX_RST

Resets MAC receiver

DEV10G::DEV_RST_CTRL.MAC_TX_RST

Resets MAC transmitter

DEV10G::DEV_RST_CTRL.PCS_RX_RST

Resets PCS receiver

DEV10G::DEV_RST_CTRL.PCS_TX_RST

Resets PCS transmitter

Table 20 •

DEV10G Interrupt Sources Registers Overview

Target::Register.Field

Description

DEV10G::INTR. PCS_BR_INTR

One of the Base-R PCS interrupt indications is active

DEV10G::INTR.TX_LPI_INTR

TX low power idle mode has changed

DEV10G::INTR.RX_LPI_INTR

RX low power idle mode has changed

DEV10G::INTR.LINK_UP_INTR

Link status is up

DEV10G::INTR. LINK_DWN_INTR

Link status is down

Table 21 •

DEV10G BASE-R PCS Interrupt Sources Registers Overview

Interrupt Mask Register

Interrupt Register Sticky Bit

Replication

PCS_INTR_MASK

SFI PCS sticky bits

Per PCS

KR_FEC_STICKY_MASK

KR FEC sticky bits

Per PCS

EEE_INTR_MASK

SFI PCS EEE sticky bits

Per PCS

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