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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VSC7440 датащи(PDF) 55 Page - Microsemi Corporation |
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VSC7440 датащи(HTML) 55 Page - Microsemi Corporation |
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55 / 444 page  Functional Descriptions VMDS-10492 VSC7440 Datasheet Revision 4.2 38 3.9.1.1 Clock and Reset There is a number of resets in the port module. All of the resets can be set and cleared simultaneously. By default, all blocks are in the reset state. With reference to DEV_RST_CTRL register, the resets are as listed in the following table. When changing the MAC configuration, the port must go through a reset cycle. This is done by writing register DEV_RST_CTRL twice. On the first write, the reset bits are set. On the second write, the reset bits are cleared. The non-reset field DEV_RST_CTRL.SPEED_SEL must keep its new value for both writes. 3.9.1.2 Interrupts The following table lists the eight interrupt sources defined for DEV1G and DEV2G5 port modules. For more information about general interrupt handling, see Interrupt Controller, page 364. MAC_MODE_CFG Port mode configuration Per port module MAC_MAXLEN_CFG Maximum length configuration Per port module MAC_TAGS_CFG VLAN/service tag configuration Per port module MAC_TAGS_CFG2 VLAN/service tag configuration 2 Per port module MAC_ADV_CHK_CFG Configuration to enable dropping of Type/Length error frames Per port module MAC_IFG_CFG Inter-frame gap configuration Per port module MAC_HDX_CFG Half-duplex configuration Per port module MAC_STICKY Sticky bit recordings Per port module Table 10 • DEV1G and DEV2G5 Reset Register.Field Description DEV_RST_CTRL.MAC_RX_RST Reset MAC receiver DEV_RST_CTRL.MAC_TX_RST Reset MAC transmitter DEV_RST_CTRL.PCS_RX_RST Reset PCS receiver DEV_RST_CTRL.PCS_TX_RST Reset PCS transmitter Table 11 • DEV1G and DEV2G5 Interrupt Sources Register Overview Register.Field Description DEV1G_INTR.FEF_FOUND_INTR_STICKY Far-end-fault indication found DEV1G_INTR.TX_LPI_INTR_STICKY Low power idle transmit interrupt DEV1G_INTR.RX_LPI_INTR_STICKY Low power idle receive interrupt DEV1G_INTR.AN_PAGE_RX_INTR_STICKY New page event received by ANEG DEV1G_INTR.AN_LINK_UP_INTR_STICKY ANEG - Link status has changed to up DEV1G_INTR.AN_LINK_DWN_INTR_STICKY ANEG - Link status has changed to down DEV1G_INTR.LINK_UP_INTR_STICKY Link status is up DEV1G_INTR. LINK_DWN_INTR_STICKY Link status is down Table 9 • DEV1G and DEV2G5 MAC Configuration Registers Overview (continued) Register Description Replication |
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