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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VSC7440 датащи(PDF) 65 Page - Microsemi Corporation |
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VSC7440 датащи(HTML) 65 Page - Microsemi Corporation |
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65 / 444 page  Functional Descriptions VMDS-10492 VSC7440 Datasheet Revision 4.2 48 By setting PCS_10GBASE_R::PCS_CFG.TX_TEST_MODE and PCS_10GBASE_R::PCS_CFG.RX_TEST_MODE register bits to 1, test pattern mode is enabled in SFI PCS. The following test patterns are supported as per IEEE 802.3, clause 49.2.8 and clause 49.2.12. • Square wave • Pseudo random • PRBS31 • User defined User-defined mode is a slightly modified test pattern in which the scrambler is not initialized with any seed value, so there will be no errors after every 128-block window. Different types of test pattern generation can be chosen by configuring PCS_10GBASE_R::TEST_CFG.TX_TESTPAT_SEL and that of checkers by configuring PCS_10GBASE_R::TEST_CFG.RX_TESTPAT_SEL. For square wave test pattern generation, period can be configured using PCS_10GBASE_R::TEST_CFG.TX_SQPW_4B. For pseudo-random test pattern inversion of seeds and data is enabled by PCS_10GBASE_R::TEST_CFG.TX_DSBL_INV and PCS_10GBASE_R::TEST_CFG.RX_DSBL_INV. 3.10.2.6 Low Power Idle The following table lists the configuration and status registers related to EEE in PCS. 3.10.2.7 KR FEC SFI PCS also supports KR FEC. The following table lists the applicable registers. PCS_10GBASE_R::PCS_STATUS.TESTP AT_MATCH When in test pattern check mode, this bit will read 1 if the test pattern checker detects a match. When 0, the test pattern does not match. The test pattern error counts should still be used along with this register bit to determine proper test match status. The bit will read back 1 only when the test pattern is matching. This may happen even while test pattern errors are counted on other clock cycles. Per PCS PCS_10GBASE_R::TEST_ERR_CNT.TES T_ERR_CNT Count of detected test pattern errors in Rx test pattern checker. Write 0 to clear. Per PCS Table 27 • DEV10G PCS EEE Configuration and Status Registers Overview Target::Register Description Replication PCS_10GBASE_R::EEE_STATUS SFI PCS low power idle status. Per PCS PCS_10GBASE_R::WAKE_ERR_CNT SFI PCS wake_error_counter value as specified in IEEE 802.3az, clause 49.2.13.2.4. Per PCS Table 28 • DEV10G KR FEC Configuration and Status Registers Overview Register Description Replication KR_FEC_CFG KR FEC configuration register Per PCS KR_FEC_STATUS KR FEC status Per PCS KR_FEC_STICKY KR FEC sticky bits Per PCS KR_FEC_CORRECTED KR FEC corrected error blocks counter Per PCS KR_FEC_UNCORRECTED KR FEC uncorrected error blocks counter Per PCS Table 26 • DEV10G BASE-R PCS Test Pattern Configuration Registers Overview (continued) Target::Register.Field Description Replication |
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