VSC7440 datasheet(52/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

Figure 14 •

ActiPHY State Diagram

3.8.6.1

Low Power State

All major digital blocks are powered down in the lower power state.

In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low

power state and transitions to the normal operating state when signal energy is detected on the media.

This happens when the PHY is connected to one of the following:

•

Auto-negotiation capable link partner

•

Another PHY in enhanced ActiPHY LP wake-up state

In the absence of signal energy on the media pins, the PHY transitions from the low power state to the

LP wake-up state periodically based on the programmable sleep timer

(PHY_CTRL_EXT3.ACTIPHY_SLEEP_TIMER). The actual sleep time duration is random, from –80 ms

to 60 ms, to avoid two linked PHYs in ActiPHY mode entering a lock-up state during operation.

After sending signal energy on the relevant media, the PHY returns to the low power state.

3.8.6.2

Link Partner Wake-up State

In the link partner wake-up state, the PHY attempts to wake up the link partner. Up to three complete FLP

bursts are sent on alternating pairs A and B of the Cat5 media for a duration based on the wake-up timer,

which is set using register bits 20E1.12:11.

After sending signal energy on the relevant media, the PHY returns to the low power state.

3.8.6.3

Normal Operating State

In normal operation, the PHY establishes a link with a link partner. When the media is unplugged or the

link partner is powered down, the PHY waits for the duration of the programmable link status time-out

timer, which is set using ACTIPHY_LINK_TIMER_MSB_CFG and ACTIPHY_LINK_TIMER_LSB_CFG in

the PHY_AUX_CTRL_STAT register. It then enters the low power state.

3.8.7

Testing Features

The integrated transceivers include several testing features designed to facilitate performing system-

level debugging.

3.8.7.1

Ethernet Packet Generator (EPG)

The Ethernet Packet Generator (EPG) can be used at each of the 10/100/1000BASE-T speed settings

for copper Cat5 media to isolate problems between the MAC and the PHY, or between a local PHY and

its remote link partner. Enabling the EPG feature effectively disables all MAC interface transmit pins and

selects the EPG as the source for all data transmitted onto the twisted pair interface.

Low Power State

LP Wake-up

State

Normal

Operation State

Signal Energy Detected on

Media

Timeout Timer Expires and

Auto-negotiation Enabled

Sleep Timer Expires

FLP Burst or

Clause 37 Restart

Signal Sent

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