VSC7440 datasheet(63/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

DEV10G::MAC_LFS_CFG.LFS_MODE_ENA. It is also possible to configure MAC into unidirectional

mode according to IEEE 802.3, Clause 66, where frames are transmitted while receiving link fault

indication but interleaved by appropriate ordered sets in between

(DEV10G::MAC_LFS_CFG.LFS_UNIDIR_ENA).

3.10.2

Physical Coding Sublayer (PCS)

This section describes the Physical Coding Sublayer (PCS) blocks included in the DEV10G port module.

The following table lists the applicable registers for DEV10G PCS configuration.

The following table lists the applicable registers for DEV10G PCS status.

3.10.2.1 Backplane Auto-Negotiation

Backplane auto-negotiation must be used when normal auto-negotiation is disabled. For the DEV10G

port module there is no specific function or setup available.

3.10.2.2 Link Surveillance

For SFI mode of operation, current link status can be observed through

PCS_10GBASE_R::PCS_STATUS defined as follows:

To receive correct data, the PCS must achieve block lock

(PCS_10GBASE_R::PCS_STATUS.RX_BLOCK_LOCK). This block lock is achieved when PCS detects

a 66-bit boundary. Whenever the block lock is lost or achieved, a sticky bit is set

(PCS_10GBASE_R::PCS_INTR_STAT.LOCK_CHANGED_STICKY). Whenever a large number of false

sync headers is detected HI_BER (PCS_10GBASE_R::PCS_STATUS.RX_HI_BER) is asserted and a

sticky bit is set (PCS_10GBASE_R::PCS_INTR_STAT.RX_HI_BER_STICKY). If a local fault or remote

fault is received, it is flagged in PCS_10GBASE_R::PCS_INTR_STAT.RX_OSET_STICKY, and the

sequence ordered set received can be read from

PCS_10GBASE_R::RX_OSET_FIFO_DATA.RX_OSET_FIFO_DATA.

Table 24 •

DEV10G PCS Configuration Registers Overview

Description

Replication

PCS_CFG

SFI-PCS configuration

Per PCS

PCS_SD_CFG

SFI-PCS signal detect configuration

Per PCS

Table 25 •

DEV10G PCS Status Registers Overview

Description

Replication

PCS_STATUS

SFI-PCS status

Per PCS

TX_ERRBLK_CNT

SFI-PCS counter for number of times transmit FSM enters TX_E state Per PCS

TX_CHARERR_CNT

SFI-PCS counter for number of invalid control characters transmitter

detected from MAC

Per PCS

RX_BER_CNT

SFI-PCS counter for number of times receive BER FSM enters

BER_BAD_SH state (ber_count)

Per PCS

RX_ERRBLK_CNT

SFI-PCS counter for number of times receive FSM enters RX_E state Per PCS

RX_CHARERR_CNT

SFI-PCS counter for receive number of invalid control characters after

decoding

Per PCS

RX_OSET_FIFO_STAT

SFI-PCS receive ordered set FIFO status

Per PCS

RX_OSET_FIFO_DATA

SFI-PCS receive ordered set FIFO data

Per PCS

RX_FSET_FIFO_STAT

SFI-PCS receive F-Sig FIFO status

Per PCS

RX_FSET_FIFO_DATA

SFI-PCS receive F-Sig FIFO data

Per PCS

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