VSC7440 datasheet(62/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

3.10.1.3 Port Mode Configuration

The MAC provides a number of handles for configuring the port mode. The following table lists the

associated registers.

3.10.1.4 Type/Length Check

The MAC supports frame lengths of up to 14,000 bytes. The maximum frame accepted by the MAC is

configurable and defined in DEV10G::MAC_MAXLEN_CFG.MAX_LEN. Maximum length is automatically

adjusted if one or more tags are included in the current frame. The MAC allows 1/2/3 tagged frames to be

4/8/12 bytes longer respectively, than the specified maximum length.

DEV10G::MAC_MAXLEN_CFG.MAX_LEN_TAG_CHK configures whether the max Length check takes

the number of tags into consideration.

A number of tags can be selected by DEV10G::MAC_NUM_TAGS_CFG.NUM_TAGS. By default,

EtherType 0x8100 and 0x88A8 are identified as VLAN tags. In addition, three custom EtherTypes can be

configured by MAC_TAGS_CFG.TAG_ID.

If a received frame exceeds the maximum length, the frame is truncated and marked as aborted.

The MAC can drop the frames with length (in-range and out-of-range) errors by enabling

MAC_ADV_CHK_CFG.INR_ERR_ENA and MAC_ADV_CHK_CFG.OOR_ERR_ENA.

There are also other checks available that can be enabled based on configurations listed in the following

table.

3.10.1.5 Local and Remote Fault Signaling

By default the MAC is configured to detect a Link Fault indication and react by transmitting the

appropriate sequence ordered set. The feature can be disabled completely using

Table 22 •

DEV10G Port Mode Configuration Registers Overview

Target::Register.Field

Description

DEV10G::DEV_RST_CTRL.SPEED_SEL

Configures MAC and PCS Rx/Tx clock frequencies.

6: Both MAC and PCS Rx/Tx clocks are disabled.

7: SFI 10 Gbps.

Unused values are reserved.

DEV10G::MAC_ENA_CFG.RX_ENA

Enable MAC receiver module.

DEV10G::MAC_ENA_CFG.TX_ENA

Enable MAC transmitter module.

DEV10G::MAC_MODE_CFG.TUNNEL_PAUSE_FRAMES

Enable tunneling of pause frames on a link.

DEV10G::MAC_MODE_CFG.MAC_PREAMBLE_CFG

Preamble format configuration.

DEV10G::MAC_MODE_CFG.MAC_IPG_CFG

IPG format configuration.

DEV10G::MAC_MODE_CFG. HIH_CRC_CHECK

Enable check for HiH checksum.

Table 23 •

DEV10G Port Module Advance Checks Configuration Registers

Target::Register.Field

Description

DEV10G::MAC_ADV_CHK_CFG.EXT_EOP_CHK_ENA

Enables extended end of packet check.

DEV10G::MAC_ADV_CHK_CFG.EXT_SOP_CHK_ENA

Enable extended start of packet check.

DEV10G::MAC_ADV_CHK_CFG.SFD_CHK_ENA

Enable start-of-frame-delimiter check.

DEV10G::MAC_ADV_CHK_CFG.PRM_SHK_CHK_DIS

Disable preamble shrink check.

DEV10G::MAC_ADV_CHK_CFG.PRM_CHK_ENA

Enable preamble check.

DEV10G::MAC_ADV_CHK_CFG.OOR_ERR_ENA

Enable out-of-range error check.

DEV10G::MAC_ADV_CHK_CFG.INR_ERR_ENA

Enable in-range error check.

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