VSC7440 datasheet(30/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

one-step clocks, a precise time is calculated and stamped directly into the PTP frames at departure. For

two-step clocks, a precise time is simply recorded and provided to the CPU for further processing. The

CPU can then initiate a follow-up message with the recorded timing.

The device supports PTP Delay_req/Delay_resp processing in hardware where the Delay_req frame is

terminated, and a Delay_resp frame is generated based on the request. In addition to updating relevant

PTP time stamps and message fields, the frame encapsulation can be changed. This includes swapping

and rewriting MAC addresses, IP addresses, and TCP/UDP ports, and updating the IPv4 TTL or IPv6

hop limit.

The device also supports generation of PTP Sync frames using the automatic frame injector (AFI)

functionality.

PTP is supported for a range of encapsulations including the following:

•

PTP over Ethernet

•

PTP over UDP over IPv4/IPv6 over Ethernet

•

Either of the above encapsulations over MPLS pseudowire over Ethernet

•

PTP over UDP over IPv4/IPv6 over MPLS over Ethernet

Two separate timing domains are supported: one for Synchronous Ethernet and data path forwarding,

and one for PTP timing synchronization. This gives the system designer control over how these two

timing architectures interact.

3.2.11

CPU Subsystem

The device contains a powerful, 500 MHz MIPS24KEc-compatible microprocessor, a high bandwidth

Ethernet Frame DMA engine, and a DDR3/DDR3L controller supporting up to 1 gigabyte (GB) of

memory. This complete system-on-chip supports Linux or embedded operating systems, enabling full

management of the switch and advanced software applications.

The device supports external CPU register access by the on-chip PCIe 1.x endpoint controller, by

specially formatted Ethernet frames on the NPI port (Versatile Register Access Protocol), or by register

access interface using SPI protocol. External CPUs can inject or extract Ethernet frames by the NPI port,

by PCIe DMA access, or by register read/writes (using any register-access interface).

3.3

Frame Headers

This section describes the internal header formats used within the device that are visible in frames to and

from the CPU, NPI port, and in frames exchanged between devices in multichip configurations.

The header formats are internal frame header (IFH) and VStaX header.

•

Internal frame header (IFH) IFH is used when extracting frames to CPU and injecting frames from

CPU. The IFH can also be inserted into frames transmitted on the NPI port. The IFH includes a

VStaX header.

•

VStaX header The VStaX header can be used for transmission to and from an NPI port.

3.3.1

Internal Frame Header Placement

The following illustration shows internal frame header placement.

Figure 4 •

Frame with Internal Frame Header

DMAC

SMAC

Frame data

Bit 0

No Prefix:

Short Prefix:

Internal Frame Header

Bit 223

ANY DMAC

Any SMAC

Bit 0

Internal Frame Header

Bit 223

0x0009

0x8880

Long Prefix:

Bit 0

Internal Frame Header

Bit 223

0x0009

0x8880

VLAN tag

Field removed before transmitted

DMAC

SMAC

Frame data

DMAC

SMAC

Frame data

ANY DMAC

Any SMAC

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