VSC7440 datasheet(54/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

3.8.7.5

Connector Loopback

The connector loopback testing feature allows the twisted pair interface to be looped back externally.

When using the connector loopback feature, the PHY must be connected to a loopback connector or a

loopback cable. Pair A must be connected to pair B, and pair C to pair D, as shown in the following

illustration. The connector loopback feature functions at all available interface speeds.

Figure 17 •

Connector Loopback Diagram

When using the connector loopback testing feature, the device auto-negotiation, speed, and duplex

configuration is set using device registers 0, 4, and 9. For 1000BASE-T connector loopback, the

following additional writes are required, executed in the following steps:

Enable the 1000BASE-T connector loopback. Set

PHY_CTRL_EXT2.CON_LOOPBACK_1000BT_ENA to 1.

Disable pair swap correction. Set PHY_CTRL_EXT2.CON_LOOPBACK_1000BT_ENA to 1.

3.8.8

VeriPHY™ Cable Diagnostics

The integrated transceivers include a comprehensive suite of cable diagnostic functions that are

available through the on-board processor. These functions enable cable operating conditions and status

to be accessed and checked. The VeriPHY suite has the ability to identify the cable length and operating

conditions and to isolate common faults that can occur on the Cat5 twisted pair cabling.

For the functional details of the VeriPHY suite and the operating instructions, see the ENT-AN0125, PHY,

Integrated PHY-Switch VeriPHY - Cable Diagnostics Feature

Application Note.

3.9

DEV1G and DEV2G5 Port Modules

The DEV1G and DEV2G5 port modules are essentially the same with identical configurations. The only

difference is the bandwidth of the bus connecting the port module to the assembler. A DEV2G5 port

module can forward data at 2.5 Gbps while the DEV1G port module can forward data at 1 Gbps. The

bandwidth of the port module is configured in the SERDES macro connecting to the port module.

3.9.1

MAC

This section describes the high level functions and configuration options of the Media Access controller

(MAC) used in the DEV1G and DEV2G5 port modules.

The DEV1G MAC supports 10/100/1000 Mbps in full-duplex mode and 10/100 Mbps in half-duplex

mode.

For the DEV2G5 MAC, the supported speeds and duplex modes depend on the following associated

SERDES macro:

•

SERDES1G: 10/100/1000 Mbps in full-duplex mode and 10/100 Mbps in half-duplex mode.

•

SERDES6G: 10/100/1000/2500 Mbps in full-duplex mode and 10/100 Mbps in half-duplex mode.

•

SERDES10G: 10/100/1000/2500 Mbps in full-duplex mode and 10/100 Mbps in half-duplex mode.

The following table lists the registers associated with configuring the MAC.

Table 9 •

DEV1G and DEV2G5 MAC Configuration Registers Overview

Description

Replication

MAC_ENA_CFG

Enabling of Rx and Tx data paths

Per port module

PHY

Switch

Cat5

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