VSC7440 datasheet(41/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

3.4

Port Numbering and Mappings

The switch core contains an internal port numbering domain where ports are numbered from 0 through

14. A port connects to a port module, which connects to an interface macro, which connects to I/O pins

on the device. The port modules are DEV2G5 or DEV10G. The interface macros are SERDES1G,

SERDES6G, SERDES10G, or a copper transceiver.

Some ports are internal to the device and do not connect to port modules or interface macros. For

example, internal ports are used for frame injection and extraction to the CPU queues.

The following table shows the default port numbering and how the ports map to port modules and

interface macros.

SRC

SRC_ADDR_MODE 10

1 bit

0: src_ind_port:

Individual port. Source consists of src_upsid and

src_upspn.

1: src_glag: Source consists of src_glag.

SRC_PORT_TYPE 11

1 bit

Only applicable if src_addr_mode==src_ind_port.

Reserved and must be set to 0 if

src_addr_mode==src_glag.

0: port_type_upspn.

1: port_type_intpn.

SRC_UPSID

9:5

5 bits

If src_addr_mode = src_ind_port:

ID of stack unit port set, where the frame was

initially received.

SRC_UPSPN

4:0

5 bits

If src_addr_mode = src_ind_port and

src_port_type = port_type_upspn:

Logical port number of the port (on source ups),

where the frame was initially received.

SRC_INTPN

3:0

4 bits

If src_addr_mode = src_ind_port and

src_port_type = port_type_intpn:

Internal port number.

SRC_GLAGID

5 bits

If src_addr_mode = src_glag:

ID of the GLAG.

Table 4 •

Default Port Numbering and Port Mappings

Port Number

Port Module

Maximum

Port Speed

Interface Macro

DEV2G5_0

1 Gbps

SERDES1G_0 or CUPHY_0

DEV2G5_1

1 Gbps

SERDES1G_1 or CUPHY_1

DEV2G5_2

1 Gbps

SERDES1G_2

DEV2G5_3

1 Gbps

SERDES1G_3

4 (NPI)

DEV2G5_4

1 Gbps

SERDES1G_4

DEV2G5_5

2.5 Gbps

SERDES6G_0

DEV2G5_6

2.5 Gbps

SERDES6G_1

DEV2G5_7

2.5 Gbps

SERDES10G_0

DEV2G5_8

2.5 Gbps

SERDES10G_1

DEV10G_0

10 Gbps

SERDES10G_2

Table 3 •

VStaX Header Fields (continued)

Field Category

Field Name

Bit

Width

Description

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