VSC7440 datasheet(73/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

access the cache using the VCAP configuration registers VCAP_ENTRY_DAT, VCAP_MASK_DAT,

VCAP_ACTION_DAT, and VCAP_CNT_DAT.

The following illustration shows an example cache register mapping for a VCAP with 36-bit entry

data/mask, 70-bit action, and a 1-bit sticky counter. Cache registers are replicated to accommodate fields

that are wider than 32 bits. For example, if the entry size is 36 bits, bits [31:0] are accessed using

VCAP_ENTRY_DAT[0][31:0], and bits [35:32] are accessed using VCAP_ENTRY_DAT[1][3:0].

Figure 19 •

VCAP Cache Layout Example

Entries have both entry data and entry mask fields. This allows a don’t-care of any bit position in the key

when matching a key against entries.

When programming a rule that does not use all the available bits in the cache, remaining (undefined)

entry bits must be set to match-0, and action bits must be set to zeros.

Table 39 •

Entry Bit Encoding

VCAP_ENTRY_DAT[n]/V

CAP_MASK_DAT[n]

Description

0/0

Bit n is encoded for the match-0 operation. When a key is applied to the VCAP, this bit

in the entry will match a 0 at position n in the key.

0/1

Bit n is encoded for match-any operation. When a key is applied to the VCAP, this bit in

the entry will match both 0 and 1 at position n in the key.

This encoding is sometimes referred to as don’t care.

1/0

Bit n is encoded for match-1 operation. When a key is applied to the VCAP, this bit in

the entry will match a 1 at position n in the key.

1/1

Bit n is encoded for match-off operation. The entry will never match any keys.

This encoding is not available in the VCAP ES0. Instead, it is treated as match-any.

VCAP_ENTRY_DAT

VCAP_MASK_DAT

VCAP_ACTION_DAT

idx: 0

idx: 1

idx: 0

idx: 1

idx: 0

idx: 1

VCAP_CNT_DAT

idx: 0

Entry Data

Entry Mask

Action

Counter

idx: 2

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