VSC7440 datasheet(56/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

3.9.1.3

Port Mode Configuration

The MAC provides a number of handles for configuring the port mode. With reference to the

MAC_MODE_CFG, MAC_IFG_CFG, and MAC_ENA_CFG registers, the handles are as listed in the

following table.

Clearing MAC_ENA_CFG.RX_ENA stops the reception of frames and further frames are discarded. An

ongoing frame reception is interrupted.

Clearing MAC_ENA_CFG.TX_ENA stops the dequeueing of frames from the egress queues, which

means that frames are held back in the egress queues. An ongoing frame transmission is completed.

TX inter-frame gap (MAC_IFG_CFG.TX_IFG) must be set according to selected speed and mode to

achieve 12 bytes IFG.

3.9.2

Half-Duplex Mode

The following special configuration options are available for half-duplex (HDX) mode.

•

Seed for back-off randomizer. MAC_HDX_CFG.SEED seeds the randomizer used by the back-off

algorithm. Use MAC_HDX_CFG.SEED_LOAD to load a new seed value.

•

Retransmission of frame after excessive collision.

MAC_HDX_CFG.RETRY_AFTER_EXC_COL_ENA determines whether the MAC retransmits

frames after an excessive collision has occurred. If set, a frame is not dropped after excessive

collisions, but the back-off sequence is restarted. This is a violation of IEEE 802.3, but is useful in

non-dropping half-duplex flow control operation.

•

Late collision timing. MAC_HDX_CFG.LATE_COL_POS adjusts the border between a collision

and a late collision in steps of 1 byte. According to IEEE 802.3, section 21.3, this border is permitted

to be on data byte 56 (counting frame data from 1); that is, a frame experiencing a collision on data

byte 55 is always retransmitted, but it is never retransmitted when the collision is on byte 57. For

each higher LATE_COL_POS value, the border is moved 1 byte higher.

•

Rx-to-Tx inter-frame gap. The sum of MAC_IFG_CFG.RX_IFG1 and MAC_IFG_CFG.RX_IFG2

establishes the time for the Rx-to-Tx inter-frame gap. RX_IFG1 is the first part of half-duplex Rx-to-

Tx inter-frame gap. Within RX_IFG1, this timing is restarted if carrier sense (CRS) has multiple high-

low transitions (due to noise). RX_IFG2 is the second part of half-duplex Rx-to-Tx inter-frame gap.

Within RX_IFG2, transitions on CRS are ignored.

3.9.2.1

Type/Length Check

The MAC supports frame lengths of up to 14,000 bytes. The maximum frame accepted by the MAC is

configurable and defined in MAC_MAXLEN_CFG.MAX_LEN.

The MAC allows 1/2/3 tagged frames to be 4/8/12 bytes longer respectively, than the specified maximum

length, with MAC_TAGS_CFG.VLAN_LEN_AWR_ENA. The MAC must be configured to look for VLAN

tags (MAC_TAGS_CFG.VLAN_AWR_ENA). By default, EtherType 0x8100 and 0x88A8 are identified as

VLAN tags. In addition, three custom EtherTypes can be configured by MAC_TAGS_CFG.TAG_ID,

MAC_TAGS_CFG2.TAG_ID2, and MAC_TAGS_CFG2.TAG_ID3.

If a received frame exceeds the maximum length, the frame is truncated and marked as aborted.

The MAC can drop frames with in-range and out-of-range length errors by enabling

MAC_ADV_CHK_CFG.LEN_DROP_ENA.

Table 12 •

DEV1G and DEV2G5 Port Mode Configuration Registers Overview

Description

MAC_MODE_CFG.FDX_ENA

Enables full-duplex mode

MAC_ENA_CFG.RX_ENA

Enables MAC receiver module

MAC_ENA_CFG.TX_ENA

Enables MAC transmitter module

MAC_IFG_CFG.TX_IFG

Adjusts inter frame gap in Tx direction

DEV_RST_CTRL.SPEED_SEL

Configures port speed and data rate

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