VSC7440 datasheet(58/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

After the last next page has been received, the auto-negotiation state machine enters the IDLE_DETECT

state, and the PCS1G_ANEG_STATUS.PR bit is set indicating that ability information exchange (base

page and possible next pages) has finished and software can now resolve priority. Appropriate actions,

such as Rx or Tx reset or auto-negotiation restart, can then be taken based on the negotiated abilities.

The LINK_OK state is reached one link timer period later.

When the auto-negotiation process reached the LINK_OK state,

PCS1G_ANEG_STATUS.ANEG_COMPLETE is asserted.

3.9.3.2

Link Surveillance

The current link status can be observed through PCS1G_LINK_STATUS.LINK_STATUS. The

LINK_STATUS is defined as either the PCS synchronization state or as bit 15 of

PCS1G_ANEG_STATUS.LP_ADV_ABILITY, which carries information about the link status in SGMII

mode.

Link down is defined as the auto-negotiation state machine being in neither the AN_DISABLE_LINK_OK

state nor the LINK_OK state for one link timer period. If a link down event occurred,

PCS1G_STICKY.LINK_DOWN_STICKY is set and PCS1G_LINK_DOWN_CNT is incremented. In

SGMII mode, the link timer period is 1.6 ms, whereas in SerDes mode, the link timer period is 10 ms.

The PCS synchronization state can be observed through PCS1G_LINK_STATUS.SYNC_STATUS.

Synchronization is lost when the PCS is not able to recover and decode data received from the attached

serial link.

3.9.3.3

Signal Detect

The PCS can be enabled to react to loss of signal through signal detect (PCS1G_SD_CFG.SD_ENA).

Upon loss of signal, the PCS Rx state machine is restarted, and frame reception stops. If signal detect is

disabled, no action is taken upon loss of signal. The polarity of signal detect is configurable in

PCS1G_SD_CFG.SD_POL.

The source of signal detect is selected in PCS1G_SD_CFG.SD_SEL to either the SerDes PMA or the

PMD receiver. If the SerDes PMA is used as source, the SerDes macro provides the signal detect. If the

PMD receiver is used as source, signal detect is sampled externally through one of the GPIO pins on the

device. For more information about the configuration of the GPIOs and signal detect, see Parallel Signal

Detect, page 354.

PCS1G_LINK_STATUS.SIGNAL_DETECT contains the current value of the signal detect input.

3.9.3.4

Tx Loopback

For debug purposes, the Tx data path in the PCS can be looped back into the Rx data path. This is

enabled through PCS1G_LB_CFG.TBI_HOST_LB_ENA.

3.9.3.5

Test Patterns

The following table lists the DEV1G and DEV2G5 registers associated with configuring test patterns.

PCS1G_TSTPAT_MODE_CFG.JTP_SEL overwrites normal operation of the PCS and enables

generation of jitter test patterns for debug. The jitter test patterns are defined in IEEE 802.3, Annex 36A.

The following patterns are supported.

•

High frequency test pattern

•

Low frequency test pattern

•

Mixed frequency test pattern

•

Continuous random test pattern with long frames

•

Continuous random test pattern with short frames

Table 14 •

DEV1G and DEV2G5 PCS Test Pattern Configuration Registers

Description

Replication

PCS1G_TSTPAT_MODE_CFG

Test pattern configuration

Per PCS

PCS1G_TSTPAT_STATUS

Test pattern status

Per PCS

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