VSC7440 datasheet(29/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

the frame’s COS and color indications such as DEI, PCP, and DSCP. Departure statistics are also kept

based on the classified VLAN.

•

Basic VLAN Tagging Operations (Port-based) By default, the egress VLAN actions are

determined by the egress port settings and classified VLAN. These include basic VLAN operations

such as pushing a VLAN tag, untagging for specific VLANs, and simple translations of DEI, PCP,

and DSCP.

•

Advanced VLAN Tagging Operations (Port-based and VCAP-based) By using the egress

VCAP ES0, significantly more advanced VLAN tagging operations can be achieved. ES0 enables

pushing up to three VLAN tags and flexible VLAN tag translation for VLAN tag/TPID, PCP, DEI, and

DSCP control. The lookup by VCAP ES0 includes classified VLAN, egress port, and COS/color

indications.

•

Layer 3 Forwarding (Routing) Operations Supports per-router-leg control of Ethernet link layer

encapsulation and VID, as well as modification of other Layer 3 fields such as IPv4 TTL, IPv4

checksum, and IPv6 hop limit.

•

PTP (IEEE 1588) Operations PTP PDU modifications include insertion/update of time stamps and

correction fields, as well as updating the UDP checksum.

The rewriter pads frames to minimum legal size if needed, and updates the FCS if the frame was

modified before the frame is transmitted.

The egress port module controls the flow control exchange of pause frames with a neighboring device

when the interconnection link operates in full-duplex flow control mode.

3.2.9

CPU Port Module

The CPU port module (DEVCPU) contains eight CPU extraction queues and two CPU injection queues.

These queues provide an interface for exchanging frames between the internal CPU system and the

switch core. An external CPU using the serial interface can also inject and extract frames to and from the

switch core by using the CPU port module.

In addition, any Ethernet interface on the device can be used for extracting and injecting frames. The

Ethernet interface used in this way is called the Node Processor Interface (NPI) and is typically

connected to an external CPU.

Injected frames may be prepended with an injection header to control processing and forwarding of these

frames. Extracted frames may be prepended with an extraction header to supply frame arrival and

classification information associated with each frame. These headers may be used by internal CPU or

external CPU.

The switch core can intercept a variety of different frame types and copy or redirect these to the CPU

extraction queues. The classifier can identify a set of well-known frames, such as IEEE reserved

destination MAC addresses (BPDUs, GARPs, CCM/Link trace), as well as IP-specific frames (IGMP,

MLD). Security VCAP IS2 provides another flexible way of intercepting all kinds of frames, such as

specific OAM frames, ARP frames or explicit applications based on TCP/UDP port numbers. In addition,

frames can be intercepted based on the MAC table, the VLAN table, or the learning process.

Whenever a frame is copied or redirected to the CPU, a CPU extraction queue number is associated with

the frame and used by the CPU port module when enqueuing the frame into the eight CPU extraction

queues. The CPU extraction queue number is programmable for every interception option in the switch

core.

3.2.10

Synchronous Ethernet and Precision Time Protocol (PTP)

The device supports Synchronous Ethernet and IEEE 1588 Precision Time Protocol (PTP) for

synchronizing network timing throughout a network.

Synchronous Ethernet allows for the transfer of precise network timing (frequency) using physical

Ethernet link timing. Each switch port can recover its ingress clock and output the recovered clock to one

of up to four recovered clock output pins. External circuitry can then generate a stable reference clock

input used for egress and core logic timing.

The Precision Time Protocol (PTP) allows for the transfer of precise network timing (frequency) and time

of day (phase) using Ethernet packets. PTP can operate as a one-step clock or a two-step clock. For

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