AD9154 datasheet(30/124 Pages) AD

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AD9154

Data Sheet

Rev. C | Page 30 of 124

CheckSumMode

CheckSumMode must match the checksum mode used on the

transmit side. If the checksum used is the sum of fields in the

link configuration table, CheckSumMode = 0. If summing the

registers containing the packed link configuration fields,

CheckSumMode = 1. For more information on the how to

calculate the two checksum modes, see the Lane0Checksum

section.

Lane0Checksum

Lane0Checksum is used for error checking purposes to ensure

that the transmitter is set up as expected.

If CheckSumMode = 0, the checksum is the lower 8 bits of the

sum of the L − 1, M − 1, K − 1, N − 1, Np − 1, S − 1, Scrambling,

HD, Subclass, and JESDVer variables.

If CheckSumMode = 1, Lane0Checksum is the lower 8 bits of

the sum of Register 0x450 to Register 0x45A. Select whether to

sum by fields or by registers, matching the setting on the

transmitter.

DAC Power-Down Setup

As described in the Step 1: Start Up the DAC section, PdDACs

must be set to 0 if all four converters are being used. If fewer

than four converters are in use, the unused converters can be

powered down. Use Table 28 determine which DACs are powered

down based on the number of converters per link (M) and

whether the device is in DualLink mode.

Table 28. DAC Power-Down Configuration Settings

M (Converters

per Link)

DualLink

DACs to Power Down

PdDACs

0b0111

0b0110

0b0011

0b0000

When using M = 1 in DualLink mode, set the I_TO_Q bit high

to ensure data entering DAC Dual B is sent to the DAC 3 output.

PdClocks

If both DACs in DAC Dual B (DAC2 and DAC3) are powered

down, the clock for DAC Dual B can be powered down. In this

case, Register 0x080, Bits[7:6] = 0x1; otherwise, Register 0x080,

Bits[7:6] = 0x0.

SERDES Clocks Setup

This section describes how to select the appropriate Halfrate,

OvSmp, and PLLDiv settings in the Step 4: Physical Layer

section. These parameters depend solely on the lane rate. The

lane rate is established in the JESD204B Setup section.

Table 29. SERDES Lane Rate Configuration Settings

Lane Rate (Gbps) (see Table 4)

Halfrate

OvSmp

PLLDiv

CDR Oversampling Mode

CDR Full Rate Mode

CDR Half Rate Mode

Halfrate and OvSmp set how the clock detect and recover

(CDR) circuit samples. See the SERDES PLL section for an

explanation of how this circuit blocks works and the role of

PLLDiv in the block.

EQUALIZATION MODE SETUP

Set EqMode = 1 for a low power setting. Select this mode if the

insertion loss in the printed circuit board (PCB) is less than

12 dB. For insertion losses greater than 12 dB but less than

17.5 dB, set EqMode = 0. See the Equalization section for more

information.

LINK LATENCY SETUP

This section describes the steps necessary to guarantee multichip

deterministic latency in Subclass 1 and guarantee synchronization

of links within a device in Subclass 0. Use this section to fill in

LMFCDel, LMFCVar, and Subclass in the Step 5: Data Link Layer

section. For more information, see the Syncing LMFC Signals

section.

Subclass Setup

The AD9154 supports JESD204B Subclass 0 and Subclass 1

operation.

Subclass 1

Subclass 1 mode achieves deterministic latency and allows the

synchronization of links to within the limits called out in Table 7.

It requires an external SYSREF± signal accurately phase aligned to

the DAC clock.

Subclass 0

Subclass 0 mode does not require any signal on the SYSREF± pins;

leave these pins disconnected.

Subclass 0 still requires that all lanes arrive within the same

LMFC cycle and the dual DACs must be synchronized to each

other (they are synchronized to an internal clock instead of the

SYSREF± signal when in Subclass 0 mode).

Set Subclass to 0 or 1 as desired.

Link Delay Setup

LMFCVar and LMFCDel impose delays such that all lanes in a

system arrive in the same LMFC cycle.

The unit used internally for delays is the period of the internal

processing clock (PClock), with a rate 1/40th of the lane rate.

Delays that are not in PClock cycles must be converted before

they are used.

Some useful internal relationships are defined below:

PClockPeriod = 40/LaneRate

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