AD9154 datasheet(73/124 Pages) AD

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Data Sheet

AD9154

Rev. C | Page 73 of 124

Use the following equation to determine the RefDivFactor:

MHz

RefDivFact

REF

(1)

where:

RefDivFactor is the reference divider division ratio.

fREF is the reference frequency on the CLK± input pins.

The BCount value is the divide ratio of the loop divider. It is set

to divide the fDACCLK to frequency match the fREF/RefDivFactor.

Select BCount so that the following equation is true:

RefDivFact

BCount

REF

DACCLK

(2)

where:

BCount is the feedback loop divider ratio.

fDACCLK is the DAC sample clock frequency.

The BCount value is programmed using Bits[7:0] of

The PFD compares fREF/RefDivRate to fDAC/(2 × BCount) and

pulses the charge pump up or down to control the frequency of

the VCO. The clock multiplication circuit operates such that the

VCO outputs a frequency, fVCO.

fVCO = fDACCLK × LoDivFactor

(3)

and from Equation 2, the DAC sample clock frequency, fDACCLK,

is equal to

RefDivFact

BCount

REF

DACCLK

= 2

(4)

The LODivFactor is chosen to keep fVCO in the operating range

between 6 GHz and 12 GHz. The valid values for LODivFactor

are 4, 8, and 16. Each LODivFactor maps to a LODIVMODE

value. The LODIVMODE (Register 0x08B[1:0]) is programmed

as described in Table 78.

Table 78. DAC VCO Divider Selection

DAC Frequency

Range (MHz)

Divide by

(LODivFactor)

LODIVMODE

>1500

750 to 1500

420 to 750

Table 79 lists some common frequency examples for the

RefDivFactor, LODivFactor, and BCount values that are needed

to configure the PLL properly.

Table 79. Common Frequency Examples

Frequency

(MHz)

fDACCLK

(MHz)

fVCO

(MHz)

RefDiv−

Factor

LODiv−

Factor

BCount

368.64

1474.56

11796.48

184.32

1474.56

11796.48

307.2

1228.88

9831.04

122.88

983.04

7864.35

61.44

983.04

7864.35

491.52

1966.08

7864.35

245.76

1966.08

7864.35

Table 79 includes different parameter sets based on fVCO. The

correct value to use is determined by the frequency into the

phase frequency detector block of the PLL.

Temperature Tracking

When properly configured, the device automatically selects one of

the 512 VCO bands. The PLL settings selected by the device ensure

that the PLL remains locked over the full −40°C to +85°C operating

temperature range of the device without further adjustment. The

PLL remains locked over the full temperature range even if the

temperature during initialization is at one of the temperature

extremes.

To properly configure temperature tracking, follow the settings

in the DAC PLL Fixed Register Writes section and the fvco

dependent SPI writes shown in Table 80.

Table 80. VCO Control Lookup Table Reference

VCO Frequency

Range (GHz)

0x1B4

Setting

0x1B6

Setting

0x1BB

Setting

fVCO < 6.85

0x60

0x49

0x15

6.85 ≤ fVCO < 8.72

0x60

0x49

0x13

8.72 ≤ fVCO < 10.7

0x60

0x4D

0x13

fVCO ≥ 10.7

0x78

0x4D

0x04

STARTING THE PLL

The programming sequence for the DAC PLL is as follows:

1. Use the equations in the Clock Multiplication

Relationships section to find fVCO, fREF, BCount,

REFDIVMODE, and LODIVMODE .

2. Program the registers in the DAC PLL Fixed Register

Writes section.

3. Program LODIVMODE into Register 0x08B, Bits[1:0].

4. Program the BCount in Register 0x085, Bits[7:0].

5. Program REFDIVMODE in Register 0x08C, Bits[2:0].

6. Based on the fVCO found in Step 1, write the temperature

tracking registers as shown in Table 80.

7. Enable the DAC PLL synthesizer by setting Register 0x083,

Bit 4 to 1.

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