 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
AD9154 датащи(PDF) 6 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9154 датащи(HTML) 6 Page - Analog Devices |
|
|
6 / 124 page  AD9154 Data Sheet Rev. C | Page 6 of 124 DIGITAL SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit CMOS INPUT LOGIC LEVEL Input Voltage (VIN) Logic High 1.8 V ≤ IOVDD ≤ 3.3 V 0.7 × IOVDD V Low 1.8 V ≤ IOVDD ≤ 3.3 V 0.3 × IOVDD V CMOS OUTPUT LOGIC LEVEL Output Voltage (VOUT) Logic High 1.8 V ≤ IOVDD ≤ 3.3 V 0.7 × IOVDD V Low 1.8 V ≤ IOVDD ≤ 3.3 V 0.3 × IOVDD V MAXIMUM DAC UPDATE RATE1 1× interpolation2 (see Table 4) 1096 MSPS 2× interpolation3 2192 MSPS 4× interpolation 2400 MSPS 8× interpolation 2400 MSPS ADJUSTED DAC UPDATE RATE 1× interpolation 1096 MSPS 2× interpolation 1096 MSPS 4× interpolation 600 MSPS 8× interpolation 300 MSPS INTERFACE4 Number of JESD204B Lanes 8 Lanes JESD204B Serial Interface Speed Minimum Per lane 1.44 Gbps Maximum Per lane, SVDD12 = 1.3 V ± 2% 10.96 Gbps DAC CLOCK INPUT (CLK±) Differential Peak-to-Peak Voltage 400 1000 2000 mV Common-Mode Voltage Self biased input, ac-coupled 600 mV Maximum Clock Rate, DAC Clock Sourced Directly from CLK± 2400 MHz PLL Multiplier Mode Clock Input Frequency5 6.0 GHz ≤ fVCO ≤ 12.0 GHz 35 1000 MHz SYSREF INPUT (SYSREF±) Differential Peak-to-Peak Voltage 400 1000 2000 mV Common-Mode Voltage 0 2000 mV SYSREF± Frequency6 fDATA/(K × (F/S)) Hz SYSREF± TO DAC CLOCK7 SYSREF± differential swing = 0.4 V, slew rate = 1.3 V/ns, (ac-coupled, and 0 V, 0.6 V, 1.25 V, 2.0 V dc-coupled common-mode voltages) Setup Time tSSD 111 ps Hold Time tHSD 145 ps SPI See timing diagrams shown in Figure 39 and Figure 40 Maximum Clock Rate SCLK IOVDD = 1.8 V 10 MHz Minimum SCLK Pulse Width High tPWH 8 ns Low tPWL 12 ns SDIO to SCLK Setup Time tDS 5 ns Hold Time tDH 2 ns SDO to SCLK Data Valid Window tDV 25 ns |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
