AD9154 datasheet(23/124 Pages) AD

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Data Sheet

AD9154

Rev. C | Page 23 of 124

Multibyte data transfers can be performed as well. Hold the CS

pin low for multiple data transfer cycles (eight SCLKs) after the

first data transfer word following the instruction cycle. The first

eight SCLKs following the instruction cycle read from or write

to the register provided in the instruction cycle. For each

additional eight SCLK cycles, the address is either incremented

or decremented and the read/write occurs on the new register.

Set the direction of the address using the address increment bits

(Register 0x000, Bit 5 and Bit 2).

When the address increment bits = 1, the multicycle addresses

are incremented. When the address increment bits = 0, the

addresses are decremented. A new write cycle can always be

initiated by bringing CS high and then low again.

During writes to Register 0x0000 only, the chip tests the first

nibble following the address phase, ignoring the second nibble.

This is completed independently from the LSB first bit and ensures

that there are extra clock cycles following the soft reset bits

(Register 0x000, Bit 0 and Bit 7).

R/W A14 A13

A0 D7N D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

Figure 37. Serial Register Interface Timing, MSB First, Address Increment Bits = 0

A12 A13 A14

D00 D10 D20

D7N

D6N

D5N

D4N

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

R/W

Figure 38. Serial Register Interface Timing, LSB First, Address Increment Bits = 1

SCLK

SDIO

DATA BIT n – 1

DATA BIT n

tDV

Figure 39. Timing Diagram for Serial Port Register Read

SCLK

SDIO

INSTRUCTION BIT 14

INSTRUCTION BIT 0

INSTRUCTION BIT 15

tSCS

tDS

tDH

tPWH

tPWL

tHCS

Figure 40. Timing Diagram for Serial Port Register Write

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