AD9154 datasheet(13/124 Pages) AD

13 / 124 page

Data Sheet

AD9154

Rev. C | Page 13 of 124

Pin No.

Mnemonic

Description

SYNCOUT0+

Positive LVDS Synchronization Output Signal for Channel Link 0.

SYNCOUT0−

Negative LVDS Synchronization Output Signal for Channel Link 0.

SERDIN2+

Serial Channel Input 2, Positive. CML compliant. SERDIN2+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN2−

Serial Channel Input 2, Negative. CML compliant. SERDIN2− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN3+

Serial Channel Input 3, Positive. CML compliant. SERDIN3+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN3−

Serial Channel Input 3, Negative. CML compliant. SERDIN3− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

LDO_BYP1

LDO SERDES Bypass. This pin requires a 1 Ω resistor in series with a 1 µF capacitor to ground.

SIOVDD33

SERDES Ports Input/Output Supply.

SERDIN4−

Serial Channel Input 4, Negative. CML compliant. SERDIN4− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN4+

Serial Channel Input 4, Positive. CML compliant. SERDIN4+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN5−

Serial Channel Input 5, Negative. CML compliant. SERDIN5− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN5+

Serial Channel Input 5, Positive. CML compliant. SERDIN5+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SYNCOUT1−

Negative LVDS Synchronization Output Signal for Channel Link 1.

SYNCOUT1+

Positive LVDS Synchronization Output Signal for Channel Link 1.

SERDIN6−

Serial Channel Input 6, Negative. CML compliant. SERDIN6− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN6+

Serial Channel Input 6, Positive. CML compliant. SERDIN6+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN7−

Serial Channel Input 7, Negative. CML compliant. SERDIN7− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN7+

Serial Channel Input 7, Positive. CML compliant. SERDIN7+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

54, 55

DNC

Do Not Connect. Do not connect to this pin.

PDP OUT1

Power Detection and Protection (PDP) Indicator for DAC2 and DAC3.

PDP OUT0

PDP Indicator for DAC0 and DAC1.

IRQ

Interrupt Request (Active Low, Open Drain).

RESET

Reset (Active Low). CMOS levels with are determined with respect to IOVDD.

SDO

Serial Port Data Output. CMOS levels with are determined with respect to IOVDD.

SDIO

Serial Port Data Input/Output. CMOS levels with are determined with respect to IOVDD.

SCLK

Serial Port Clock Input. CMOS levels with are determined with respect to IOVDD.

Serial Port Chip Select (Active Low). CMOS levels with are determined with respect to IOVDD.

IOVDD

CMOS Input/Output and SPI Pin Supply.

67, 70, 72, 75,

77, 80, 82, 85

AVDD33

3.3 V Analog Supplies for the DAC Cores.

OUT3+

DAC3 Positive Current Output.

OUT3−

DAC3 Negative Current Output.

71, 76, 81, 87

CVDD12

1.2 V Clock Supplies.

OUT2−

DAC2 Negative Current Output.

OUT2+

DAC2 Positive Current Output.

OUT1+

DAC1 Positive Current Output.

OUT1−

DAC1 Negative Current Output.

OUT0−

DAC0 Negative Current Output.

OUT0+

DAC0 Positive Current Output.

I120

Output Current Generation Pin for DAC Full-Scale Current. Tie a 4 kΩ resistor from this pin to ground.

LDO_BYP2

LDO Clock Bypass for the DAC PLL. Tie a 1 Ω resistor in series with a 1 µF capacitor from this pin to ground.

EPAD

Exposed Pad. The exposed pad must be securely connected to the ground plane.

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