AD9154 datasheet(97/124 Pages) AD

97 / 124 page

Data Sheet

AD9154

Rev. C | Page 97 of 124

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

GROUPCOMP_

BYPI

Bypass the Q Channel Group Delay Compensation

Circuitry.

0x1

R/W

GROUPCOMP_

BYPQ

Bypass the I Channel Group Delay Compensation

Circuitry.

0x1

R/W

0x04A

MIX_MODE

[7:1]

RESERVED

Reserved.

0x0

MIX_MODE

Mix Mode Enable.

0x0

R/W

0 Mix mode off.

1 Mix mode on.

0x050

NCO_

CLRMODE

NCOCLRARM

Arm NCO Clear. Arms NCO clearing operation.

0x0

R/W

1 Arm NCO clear logic.

RESERVED

Reserved.

0x0

NCOCLRMTCH

NCO Clear Data Match.

0x0

1 Key NCO clear data match.

NCOCLRPASS

NCO Clear Passed.

0x0

1 NCO clear took effect.

NCOCLRFAIL

NCO Clear Failed.

0x0

1 NCO reset during rotate.

RESERVED

Reserved.

0x0

[1:0]

NCOCLRMODE

NCO Clear Mode.

0x0

R/W

0 NCO clearing disabled.

2 NCO clear on data key.

1 NCO clear on SYSREF.

0x051

NCOKEY_ILSB

[7:0]

NCOKEYILSB

NCO DataKey for I Channel LSB.

0x0

R/W

0x052

NCOKEY_IMSB

[7:0]

NCOKEYIMSB

NCO DataKey for I Channel MSB.

0x0

R/W

0x053

NCOKEY_QLSB

[7:0]

NCOKEYQLSB

NCO DataKey for Q Channel LSB.

0x0

R/W

0x054

NCOKEY_

QMSB

[7:0]

NCOKEYQMSB

NCO DataKey for Q Channel MSB.

0x0

R/W

0x060

PA_THRES0

[7:0]

PDP_THRESHOLD

[7:0]

Average Power Threshold for Comparison.

0x0

R/W

0x061

PA_THRES1

[7:5]

RESERVED

Reserved.

0x0

[4:0]

PA_THRESHOLD_

MSB

Average Power Threshold for Comparison.

0x0

R/W

0x062

PDP_AVG_TIME 7

PDP_ENABLE

1 Enable Average Power Calculation and Error

Detection

0x0

R/W

PA_BUS_SWAP

Swap Channel A or Channel B Data Bus for Power

Calculation.

0x0

R/W

[5:4]

RESERVED

Reserved.

0x0

[3:0]

PDP_AVG_TIME

Set Power Average Time.

0x0

R/W

0x063

PA_POWER0

[7:0]

PDP_POWER[7:0]

Average Power Bus = I2 + Q2 (I/Q Use 6 MSBs of Data

Bus).

0x0

0x064

PA_POWER1

[7:5]

RESERVED

Reserved.

0x0

[4:0]

PDP_POWER[12:8]

Average Power Bus = I2 + Q2 (I/Q Use 6 MSBs of Data

Bus).

0x0

0x080

CLKCFG0

PD_CLK01

Power-Down Clock for Dual A.

0x1

R/W

0 Enable clock divider in Dual A.

1 Disable clock divider in Dual A.

PD_CLK23

Power-Down Clock for Dual B.

0x1

R/W

0 Enable clock divider in Dual B.

1 Power-down clock divider in Dual B.

PDCLOCKDIG

Power-Down Clocks to All DACs.

0x1

R/W

0 Enable clock for all DACs.

1 Power-down clock for all DACs.

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