AD9154 datasheet(91/124 Pages) AD

91 / 124 page

Data Sheet

AD9154

Rev. C | Page 91 of 124

Table 93. AD9154 Register Details

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x000

SPI_INTFCONFA 7

SOFTRESET_M

Soft Reset (Mirror).

0x0

LSBFIRST_M

LSB First (Mirror).

0x0

ADDRINC_M

Address Increment (Mirror).

0x0

SDOACTIVE_M

SDO Active (Mirror).

0x0

SDOACTIVE

SDO Active.

0x0

R/W

ADDRINC

Address Increment. When set, causes incrementing

streaming addresses; otherwise, descending

addresses are generated.

0x0

R/W

1 Streaming addresses are incremented.

0 Streaming addresses are decremented.

LSBFIRST

LSB First. When set, causes input and output data to

be oriented LSB first. If this bit is clear, data is

oriented MSB first.

0x0

R/W

1 Shift LSB in first.

0 Shift MSB in first.

SOFTRESET

Soft Reset. Setting this bit initiates a reset. This bit is

autoclearing after the soft reset is complete.

0x0

R/W

1 Pulse the soft reset line.

0 Release soft reset.

0x003

SPI_CHIPTYPE

[7:0]

CHIPTYPE

High Speed DAC.

0x4

0x004

SPI_PRODIDL

[7:0]

PRODIDL

Product ID Low.

0x54

0x005

SPI_PRODIDH

[7:0]

PRODIDH

Product ID High.

0x91

0x006

SPI_CHIP-

GRADE

[7:4]

PROD_GRADE

Product Grade.

0x9

[3:0]

DEV_REVISION

Device Revision.

0x9

0x008

DUAL_PAGE

[7:2]

RESERVED

Reserved.

0x0

[1:0]

PAGEINDX

Page or Index Pointer.

0x3

R/W

1 Select Link A.

2 Select Link B.

3 Select Link A and Link B.

0x011

PWRCNTRL0

PD_BG

Reference Power-Down.

0x1

R/W

0 Reference on.

1 Reference powered down. Overrides TXENx masked bit.

PDDAC0

PD I Channel DAC 0.

0x1

R/W

0 Enable DAC0 I channel Dual0.

1 Power down DAC0 I channel Dual0. Overrides TXENx

masked bit.

PDDAC1

PD Q Channel DAC 1.

0x1

R/W

0 Enable Q channel DAC of Dual A.

1 Power Down Q channel DAC of Dual A. Overrides

TXENx masked bit.

PDDAC2

PD I Channel DAC 2.

0x1

R/W

0 Enable I channel DAC of Dual B.

Power Down I channel DAC of Dual B. Overrides

TXENx masked bit.

PDDAC3

PD Q Channel DAC 3.

0x1

R/W

0 Enable Q channel DAC of Dual B.

1 Powers down Q channel DAC of Dual B. Overrides

TXENx masked bit.

[2:0]

RESERVED

Reserved.

0x0

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