AD9154 datasheet(9/124 Pages) AD

9 / 124 page

Data Sheet

AD9154

Rev. C | Page 9 of 124

LATENCY VARIATION SPECIFICATIONS

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V,

VTT = 1.2 V, TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.

Table 7.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DAC LATENCY VARIATION

Subclass 1

PLL Off

DACCLK cycles

PLL On

−1

DACCLK cycles

JESD204B INTERFACE ELECTRICAL SPECIFICATIONS

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V,

VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.

Table 8.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

JESD204B DATA INPUTS

Input Leakage Current

TA = 25°C

Logic High

Input level = 1.2 V ± 0.25 V, VTT = 1.2 V

µA

Logic Low

Input level = 0 V

−4

µA

Unit Interval

714

Common-Mode Voltage

VRCM

AC-coupled

−0.05

+1.85

VTT = SVDD121

Differential Voltage

R_VDIFF

110

1050

VTT Source Impedance

ZTT

At dc

Differential Impedance

ZRDIFF

At dc

100

120

Differential Return Loss

RLRDIF

Common-Mode Return Loss

RLRCM

DIFFERENTIAL OUTPUTS (SYNCOUT±)2

Output Offset Voltage

VOS

1.19

1.27

DETERMINISTIC LATENCY

Fixed

PClock3 cycles

Variable

PClock3 cycles

SYSREF± TO LOCAL MULTIFRAME

CLOCK (LMFC) DELAY

DAC clock cycles

As measured on the input side of the ac coupling capacitor.

IEEE Standard 1596.3 LVDS compatible.

PClock is the AD9154 internal processing clock; its frequency is equal to the JESD204B lane rate ÷ 40.

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