AD9154 datasheet(92/124 Pages) AD

92 / 124 page

AD9154

Data Sheet

Rev. C | Page 92 of 124

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x012

TXENMASK1

DACB_MASK

Dual 23 DAC Power-Down Mask for TXEN1.

0x0

R/W

0 Default power-down to control by power-down bit only.

1 If TXEN1 is low, DAC 2 and DAC 3 are powered down;

otherwise state of individual power-downs.

DACA_MASK

Dual 01 DAC power-down mask for TXEN0.

0x0

R/W

0 Default power-down to control by power-down bit

only.

1 If TXEN0 is low, DAC 0 and DAC 1 are powered down;

otherwise state of individual power-downs.

[5:0]

RESERVED

Reserved

0x0

R/W

0x013

PWRCNTRL3

RESERVED

Reserved.

0x0

ENA_PA_CTRL_

FROM_PAPROT_

ERR

Control PA enable from PAProt block.

0x0

R/W

ENA_PA_CTRL_

FROM_TXENSM

Control PA enable from TXEN state machine.

0x1

R/W

ENA_PA_CTRL_

FROM_BLSM

Control PA enable from blanking state machine.

0x0

R/W

ENA_PA_CTRL_

FROM_SPI

Control PA enable via SPI.

0x0

R/W

SPI_PA_CTRL

PA on/off via SPI.

0x0

R/W

ENA_SPI_TXEN

TXENx from SPI control.

0x0

R/W

SPI_TXEN

SPI TXENx.

0x0

R/W

1 TXENx SPI is high.

0 TXENx SPI is low.

0x014

COARSE_

GROUP_DLY

[7:4]

RESERVED

Reserved.

0x0

[3:0]

COARSE_

GROUP_DLY

Coarse Group Delay. The range of the delay is −4 to

+3 DAC clock periods and the resolution is 1/2 DAC

clock period.

0x8

R/W

0 minimum delay.

15 maximum delay.

0x01F

IRQ_ENABLE0

[7:6]

RESERVED

Reserved.

0x0

R/W

EN_DACPLLLOST

Enable DAC PLL Lost Detection. The DACPLLLOCK,

when enabled, shows that the DAC (clock

generation) PLL has dropped its lock state.

0x0

R/W

1 Enable DAC PLL lost.

EN_DACPLLLOCK

Enable DAC PLL Lock Detection. The DACPLLLOCK,

when enabled, shows that the DAC (clock

generation) PLL has reached a lock state.

0x0

R/W

1 Enable DAC PLL lock.

EN_SERPLLLOST

Enable SERDES PLL Lost Detection. The SERPLLLOCK,

when enabled, shows that the SERDES (JESD204B

interface) PLL has dropped its lock state.

0x0

R/W

1 Enable SERDES PLL lost.

EN_SERPLLLOCK

Enable SERDES PLL Lock Detection. The SERPLLLOCK,

when enabled, shows that the SERDES (JESD204B

interface) PLL has reached a lock state.

0x0

R/W

1 Enable SERDES PLL lock.

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